Skip to content
@merledu

Micro Electronics Research Laboratory

A non-profit organization fostering research on IoT, AI, and ML-based architectures leveraging the open-source RISC-V ISA.

Pinned

  1. OpenTCAM OpenTCAM Public

    An open-source Ternary Content Addressable Memory (TCAM) compiler.

    Python 17 9

  2. azadi-soc azadi-soc Public

    Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

    SystemVerilog 23 11

  3. Google-Summer-of-Code Google-Summer-of-Code Public

    Project ideas list for Google Summer of Code.

    12 2

  4. Ibtida Ibtida Public

    A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).

    Verilog 4 2

  5. TileLink TileLink Public

    TileLink Uncached Lightweight (TL-UL) implementation on Chisel.

    Scala 19 9

  6. buraq_mini buraq_mini Public

    This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

    Scala 8 6

Repositories

Showing 10 of 130 repositories
  • OpenTCAM Public

    An open-source Ternary Content Addressable Memory (TCAM) compiler.

    merledu/OpenTCAM’s past year of commit activity
    Python 17 Apache-2.0 9 0 1 Updated Jun 2, 2024
  • nucleusrv Public

    NucleusRV - A 32-bit 5 staged pipelined risc-v core.

    merledu/nucleusrv’s past year of commit activity
    C 57 GPL-3.0 19 9 0 Updated May 31, 2024
  • Burq-Suite Public

    An All in one RISC-V Suite.

    merledu/Burq-Suite’s past year of commit activity
    HTML 5 3 0 0 Updated May 31, 2024
  • MERL-Attendance Public
    merledu/MERL-Attendance’s past year of commit activity
    Python 0 1 0 1 Updated May 20, 2024
  • rv-thunder Public

    RISC-V 32-bit CPU written in amaranth (python-lib)

    merledu/rv-thunder’s past year of commit activity
    Verilog 7 5 1 1 Updated Apr 22, 2024
  • Merl-UIT-Simulator Public
    merledu/Merl-UIT-Simulator’s past year of commit activity
    JavaScript 1 5 0 3 Updated Mar 27, 2024
  • ArcheV Public

    RISC-V RV-32i RTL Benchmark for evaluating Large Language Models.

    merledu/ArcheV’s past year of commit activity
    Verilog 0 1 1 1 Updated Mar 26, 2024
  • xodus Public

    RV32-I 5 Stage Pipelined Core implemented in CHISEL HDL

    merledu/xodus’s past year of commit activity
    Scala 1 GPL-3.0 1 0 0 Updated Mar 23, 2024
  • magma-si Public

    Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL

    merledu/magma-si’s past year of commit activity
    Scala 8 GPL-3.0 3 4 2 Updated Mar 21, 2024
  • zeusic-v Public

    RISC-V based Neuromorphic Processor for accelerating Spiking Neural Networks

    merledu/zeusic-v’s past year of commit activity
    2 2 0 0 Updated Feb 6, 2024
View all repositories

Most used topics

Loading…