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  1. caravel_BrqRV_EB1 caravel_BrqRV_EB1 Public

    Forked from efabless/caravel_user_project

    https://caravel-user-project.readthedocs.io

    Verilog 1

  2. force-riscv force-riscv Public

    Forked from openhwgroup/force-riscv

    Instruction Set Generator initially contributed by Futurewei

    C++

  3. ava-core ava-core Public

    Forked from AI-Vector-Accelerator/ava-core

    A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)

    SystemVerilog

  4. ara ara Public

    Forked from pulp-platform/ara

    The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.9, working as a coprocessor to CORE-V's CVA6 core

    C 1

  5. apb4_gpio apb4_gpio Public

    Forked from RoaLogic/apb4_gpio

    General Purpose IO with APB4 interface

    SystemVerilog

  6. riscv_soc riscv_soc Public

    Forked from ultraembedded/riscv_soc

    Basic RISC-V Test SoC

    Verilog