Skip to content
View hadirkhan10's full-sized avatar
๐Ÿ‘‹
๐Ÿ‘‹

Organizations

@merledu
Block or Report

Block or report hadirkhan10

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this userโ€™s behavior. Learn more about reporting abuse.

Report abuse
hadirkhan10/README.md

Great to see you ๐Ÿ‘‹

  • Currently involved in VLSI-DA group at UC Santa Cruz
  • Working on Chisel based hardware designs and VLSI design automation
  • How to reach me: [email protected]

Pinned Loading

  1. picofoxy picofoxy Public

    Forked from merledu/picofoxy

    Pipelined In-order Core for Artix-7 Arty-35T board

    Scala 2

  2. caravel_ibtida_soc caravel_ibtida_soc Public

    Forked from efabless/caravel_mpw-one

    Verilog 12 3

  3. openlane-gui openlane-gui Public

    A graphical user interface for the OpenLANE RTL-GDSII flow

    Python 3

  4. caravan caravan Public

    Forked from merledu/caravan

    A caravan equipped with API for creating bus protocols in Chisel with ease.

    Scala 3

  5. TileLink TileLink Public

    Forked from merledu/TileLink

    TileLink Uncached Lightweight (TL-UL) implementation on Chisel.

    Scala 1

  6. jigsaw jigsaw Public

    Forked from merledu/jigsaw

    A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).

    Scala 1