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@merledu
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AuringzaibSabir/README.md

Hello World! 👋 I'm Auringzaib Sabir - Design Verification Engineer & Research Associate

I am (!Gold_Medalist || !Failure)

Over the last few years, I have been serving in the semiconductor industry as a hardware verification engineer. I have developed expertise in verification methodologies like UVM, System Verilog, Functional verification, Functional coverages, Python, PCIe, and CXL. I have gained considerable knowledge in the field of semiconductors.

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website website    website website

Languages and Tools:

System Verilog UVM RISC-V Python synosys cadence

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  1. azadi-verify azadi-verify Public

    Forked from merledu/azadi-verify

    This repository contains tests (in C and assembly both), benchmarks and the test-benches for the verification of Azadi SoC.

    Assembly

  2. common_peripheral_vips common_peripheral_vips Public

    Forked from merledu/common_peripheral_vips

    SystemVerilog

  3. azadi-new azadi-new Public

    Forked from merledu/azadi-soc

    Azadi after tapeout

    SystemVerilog

  4. python_project python_project Public

    Python

  5. uvm_sample uvm_sample Public

    This repository contains a sample code of the UVM environment. Use this code as a reference for writing a complex UVM framework.

    SystemVerilog 3 2