GitHub - tharunchitipolu/RISC-V-32I-based-core-with-Advanced-Extensible-Interface: 5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.

tharunchitipolu / RISC-V-32I-based-core-with-Advanced-Extensible-Interface Public

5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
5_stage_pipeline.cache		5_stage_pipeline.cache
5_stage_pipeline.hw		5_stage_pipeline.hw
5_stage_pipeline.sim/sim_1/behav/xsim		5_stage_pipeline.sim/sim_1/behav/xsim
5_stage_pipeline.srcs/sources_1/new		5_stage_pipeline.srcs/sources_1/new
pipeline_trial1_behav.wcfg		pipeline_trial1_behav.wcfg