tharunchitipolu / RISC-V-32I-based-core-with-Advanced-Extensible-Interface Star 9 Code Issues Pull requests 5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory. arm pipeline cache processor verilog systemverilog computer-architecture testbench verilog-hdl risc-v digitaldesign axi3 Updated May 28, 2022 Verilog
vaseegoo / AXI3_VIP Star 1 Code Issues Pull requests Xillinx AXI Verification IP VLNV:axi_vip1.1@Vivado 2017.4 bfm axi3 Updated Aug 3, 2018 Verilog
vaseegoo / axi_vip Star 0 Code Issues Pull requests Xillinx AXI Verification IP :axi_vip1.1@Vivado 2017.4 vip bfm xillinx axi3 Updated Aug 3, 2018 Verilog