Zen2

Architecture specific notes for AMD K17 (Zen2)

Performance groups

The following performance groups are partly based on the report by AMD fellow Paul J. Drongowski: Basic Performance Measurements for AMD Athlon™ 64, AMD Opteron™ and AMD Phenom™ Processors. The groups are mainly copied from the AMD K16 (Kabini) architecture.

AMD Zen2 Performance groups

Events

The input file for the events on AMD Zen2 can be found here.

Counters

• Core-local counters
  • Fixed-purpose counters
  • General-purpose counters
• Cache-wide counters
  • L3 general-purpose counters
• Socket-wide counters
  • Energy counters

Core-local counters

Fixed-purpose counters

The AMD® Zen2 microarchitecture provides three fixed-purpose counters for retired instructions, actual CPU core clock (MPerf: This register increments in proportion to the actual number of core clocks cycles while the core is in C0) and maximum CPU core clock (APerf: Incremented by hardware at the P0 frequency while the core is in C0).

Counters

Counter name	Event name
FIXC0	INST_RETIRED_ANY
FIXC1	ACTUAL_CPU_CLOCK
FIXC2	MAX_CPU_CLOCK

WARNING: Don't use the INST_RETIRED_ANY:FIXC0 if you can avoid it by using RETIRED_INSTRUCTIONS:PMCx

General-purpose counters

The AMD® Zen2 microarchitecture provides 6 general-purpose counters consisting of a config and a counter register.

Counters

Counter name	Event name
PMC0	*
PMC1	*
PMC2	*
PMC3	*
PMC4	*
PMC5	*

Available Options

Option	Argument	Description	Comment
edgedetect	N	Set bit 18 in config register
kernel	N	Set bit 17 in config register
threshold	8 bit hex value	Set bits 24-31 in config register	The value for threshold can range between 0x0 and 0x7F
invert	N	Set bit 23 in config register

Cache-wide counters

L3 general-purpose counters

The AMD® Zen2 microarchitecture provides 6 general-purpose counters for measuring L3 cache events. They consist of a config and a counter register. The counters are related to a shared L3 cache (or Compute Complex), hence you get only one value per L3 cache (CCX).

Counters

Counter name	Event name
CPMC0	*
CPMC1	*
CPMC2	*
CPMC3	*
CPMC4	*
CPMC5	*

Available Options

Option	Argument	Description	Comment
tid	8 bit hex value	Set bits 56 to 63 in config register.	Selects whether the accesses of an attached thread should be counted. Default all threads: 0xFF
match0	4 bit hex value	Set bits 48 to 51 in config register	Selects whether accesses to a L3 cache slice should be counted. Default all slices: 0xF

Socket-wide counters

Energy counters

The AMD® Zen2 microarchitecture provides 2 energy counters (RAPL) for CPU core and package energy. Keep in mind, that the CPU core counter returns one value per CPU core, the package counter once per CPU socket.

Counters

Counter name	Event name
PWR0	RAPL_CORE_ENERGY
PWR1	RAPL_PKG_ENERGY