Code generation tool for control and status registers
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Updated
Jun 11, 2024 - Ruby
Code generation tool for control and status registers
A small, light weight, RISC CPU soft core
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Versatile Functional Bus Description Language compiler back-end written in Go.
Wishbone controlled I2C controllers
A simple, basic, formally verified UART controller
A collection of debugging busses developed and presented at zipcpu.com
A utility for Composing FPGA designs from Peripherals
A wishbone controlled FM transmitter hack
A wishbone controlled scope for FPGA's
Bus bridges and other odds and ends
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
Simple UART controller for FPGA written in VHDL
A collection of formal properties for hardware buses, and cores using them.
A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91
RISC-V Ibex core with Wishbone B4 interface
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