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Digital logic design tool and simulator
Updated
May 13, 2024
Java
A FPGA friendly 32 bit RISC-V CPU implementation
Updated
Apr 4, 2024
Assembly
VHDL 2008/93/87 simulator
Updated
May 14, 2024
VHDL
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Updated
May 13, 2024
Python
Updated
May 13, 2024
Scala
🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Updated
May 14, 2024
VHDL
Haskell to VHDL/Verilog/SystemVerilog compiler
Updated
May 11, 2024
Haskell
Package manager and build abstraction tool for FPGA/ASIC development
Updated
Apr 28, 2024
Python
Hardware Description Languages
VUnit is a unit testing framework for VHDL/SystemVerilog
Updated
May 13, 2024
VHDL
A tiny Open POWER ISA softcore written in VHDL 2008
Updated
Apr 10, 2024
Verilog
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
Updated
Dec 6, 2023
Verilog
An abstraction library for interfacing EDA tools
Updated
May 9, 2024
Python
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Updated
Dec 21, 2023
Verilog
VHDL compiler and simulator
Updated
May 14, 2024
VHDL
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Updated
May 12, 2024
Python
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Updated
Nov 29, 2020
VHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Updated
Apr 26, 2024
JavaScript
A List of Free and Open Source Hardware Verification Tools and Frameworks
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
Updated
Apr 15, 2024
VHDL
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