rggen / rggen Star 288 Code Issues Pull requests Discussions Code generation tool for control and status registers asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents Updated May 15, 2024 Ruby
SystemRDL / PeakRDL Star 74 Code Issues Pull requests Control and status register code generator toolchain asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model Updated Nov 8, 2023 Python
SystemRDL / PeakRDL-uvm Star 45 Code Issues Pull requests Generate UVM register model from compiled SystemRDL input asic fpga eda uvm registers uvm-ral-model uvm-register-model Updated Jan 25, 2024 Python
rggen / rggen-sample-testbench Star 15 Code Issues Pull requests vhdl verilog systemverilog uvm uvm-ral-model uvm-register-model Updated May 15, 2024 VHDL
rggen / rggen-sv-ral Star 6 Code Issues Pull requests UVM RAL class package for RgGen systemverilog uvm ral uvm-ral-model uvm-register-model Updated Feb 1, 2024 SystemVerilog