stnolting / neorv32 Star 1.4k Code Issues Pull requests Discussions 🚀 A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. microcontroller embedded asic cpu fpga processor vhdl gdb riscv rtl verilog safety soc risc-v openocd soft-core system-on-chip rv32 asip neorv32 Updated May 19, 2024 VHDL
timurkelin / simsimd Star 11 Code Issues Pull requests Development and simulation framework for Application Specific Vector Processor data-driven dsp architecture simd simulation-framework digital-signal-processing cycle-accurate systemc model-based network-on-chip heterogeneous-computing vector-processor single-instruction-multiple-data asip application-specific system-simulation vector-core heterogeneous-structure system-level-simulation multimode-processing Updated Mar 8, 2020 C++
nansencenter / sea_ice_type_cnn_training Star 5 Code Issues Pull requests Deep learning of satellite data: Use the data from satellites for machine learning (deep learning) purposes inference tensorboard satellites tensorflow-training asip Updated Aug 19, 2022 Jupyter Notebook
LatifAkcayGithub / PQC-ASIP Star 0 Code Issues Pull requests TTA-based ASIP designs for PQC algorithms tce tta pqc asip Updated Feb 26, 2024