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Florin623 / AXI-Lite-Slave-FFT-IP

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3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.

design communication-protocol pipeline digital hardware electronics signal-processing processor master-slave verilog fft vivado intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis
  • Updated Apr 13, 2024
  • VHDL

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