Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

FPGA: Increase clock frequency to 21 MHz #237

Merged
merged 2 commits into from
Aug 20, 2024
Merged

FPGA: Increase clock frequency to 21 MHz #237

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
75b0285
FPGA: Increase clock frequency to 21 MHz
secworks Jun 17, 2024
7f93b78
FPGA: Add --freq constraint to nextpnr
secworks Jun 24, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 5 additions & 1 deletion hw/application_fpga/Makefile
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,10 @@ YOSYS_PATH ?=
NEXTPNR_PATH ?=
ICESTORM_PATH ?=

# FPGA target frequency. Should be in sync with the clock frequency
# given by the parameters to the PLL in rtl/clk_reset_gen.v
TARGET_FREQ ?= 21

# Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16
# bits wide; an EBR is 128 32-bits words)
BRAM_FW_SIZE ?= 1536
Expand Down Expand Up @@ -256,7 +260,7 @@ synth.json: $(FPGA_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/
$(filter %.v, $^)

application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
$(NEXTPNR_PATH)nextpnr-ice40 --ignore-loops --up5k --package sg48 --json $< \
$(NEXTPNR_PATH)nextpnr-ice40 --freq $(TARGET_FREQ) --ignore-loops --up5k --package sg48 --json $< \
--pcf $(P)/data/$(PIN_FILE) --write $@

application_fpga.asc: application_fpga_par.json $(P)/data/uds.hex $(P)/data/udi.hex
Expand Down
2 changes: 1 addition & 1 deletion hw/application_fpga/application_fpga.bin.sha256
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1 +1 @@
24e642b0dc78a7dbf4cd87c223dd26eefb1ad444c96858e1c2b373f35701ccc0 application_fpga.bin
42746c6d9d879ad975874fb51b3d4e031578dac9a0e7ddd4b10a1d3efa34c6c7 application_fpga.bin
6 changes: 3 additions & 3 deletions hw/application_fpga/core/uart/rtl/uart.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -83,10 +83,10 @@ module uart(
// The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 18 MHz, 62500 bps
// Divisor = 18E6 / 62500 = 288
// Clock: 21 MHz, 62500 bps
// Divisor = 21E6 / 62500 = 336
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd288;
localparam DEFAULT_BIT_RATE = 16'd336;
localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1;

Expand Down
10 changes: 5 additions & 5 deletions hw/application_fpga/rtl/clk_reset_gen.v
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -70,14 +70,14 @@ module clk_reset_gen #(parameter RESET_CYCLES = 200)
//
// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
//
// Given the 12 MHz HFOSC clock set above, we get a final 18 MHz:
// Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
//
// (12000000 * (47 + 1)) / (2^5 * (0 + 1)) = 18000000
// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b0101111), // DIVF = 47
.DIVQ(3'b101), // DIVQ = 5
.DIVR(4'd0), // DIVR = 0
.DIVF(7'd55), // DIVF = 55
.DIVQ(3'd5), // DIVQ = 5
.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
) pll_inst (
.RESETB(1'b1),
Expand Down