FPGA: Increase clock frequency to 21 MHz

[secworks]

FPGA clock increased to 21 MHz
UART bitrate increased to 500 kbps

[dehanj]

Testing using tkey-random-generator pushing out 1 MB of data, no bit-errors. So UART/USB transfers seems stable.

Also running long term tests, locally by using a TKey with this daily. Will continue a few days more to see how it behaves.

[dehanj]

I see a need to be able to build the bitstream with the original baudrate of 62500.
The question is how; build separate bitstream with some build flag, or let firmware decide on startup depending on what hardware/version is running.

[secworks]

I see a need to be able to build the bitstream with the original baudrate of 62500. The question is how; build separate bitstream with some build flag, or let firmware decide on startup depending on what hardware/version is running.

Should that baudrate be the default, no matter what the clock speed is? Basically what I'm asking is if the default baudrate should be independent of the clock speed, or the default baudrate is tied to to the clock speed.

The easiest, from a HW or build system point of view, is of course leave this to the FW. But otoh that adds complexity to the FW. At the same time, we want the FW to as soon as possible use the highest possible baudrate for the specific device it is running on.

We could of course create build flags and compile time defines that sets the PLL parameters to the expected clock speed. And then derive the UART clock cycle counter target to get the default baudrate based on the target clock speed. Being able to set the target clock speed is probably something we want anyway.

[dehanj]

Removed the UART baudrate change, only increasing clock frequency for this PR.