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FPGA: Increase clock frequency to 21 MHz #237

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merged 2 commits into from
Aug 20, 2024
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@secworks secworks commented Jun 17, 2024

FPGA clock increased to 21 MHz
UART bitrate increased to 500 kbps

@secworks secworks requested a review from dehanj June 17, 2024 13:31
@dehanj dehanj linked an issue Jun 17, 2024 that may be closed by this pull request
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dehanj commented Jun 18, 2024

Testing using tkey-random-generator pushing out 1 MB of data, no bit-errors. So UART/USB transfers seems stable.

Also running long term tests, locally by using a TKey with this daily. Will continue a few days more to see how it behaves.

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dehanj commented Jul 4, 2024

I see a need to be able to build the bitstream with the original baudrate of 62500.
The question is how; build separate bitstream with some build flag, or let firmware decide on startup depending on what hardware/version is running.

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secworks commented Jul 8, 2024

I see a need to be able to build the bitstream with the original baudrate of 62500. The question is how; build separate bitstream with some build flag, or let firmware decide on startup depending on what hardware/version is running.

Should that baudrate be the default, no matter what the clock speed is? Basically what I'm asking is if the default baudrate should be independent of the clock speed, or the default baudrate is tied to to the clock speed.

The easiest, from a HW or build system point of view, is of course leave this to the FW. But otoh that adds complexity to the FW. At the same time, we want the FW to as soon as possible use the highest possible baudrate for the specific device it is running on.

We could of course create build flags and compile time defines that sets the PLL parameters to the expected clock speed. And then derive the UART clock cycle counter target to get the default baudrate based on the target clock speed. Being able to set the target clock speed is probably something we want anyway.

@dehanj dehanj changed the title FPGA: Increase clock frequency and UART bitrate FPGA: Increase clock frequency to 21 MHz Aug 20, 2024
@dehanj dehanj marked this pull request as ready for review August 20, 2024 11:43
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Removed the UART baudrate change, only increasing clock frequency for this PR.

@dehanj dehanj merged commit 7f93b78 into main Aug 20, 2024
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@dehanj dehanj deleted the inc_fpga_clock_frequency branch August 20, 2024 11:52
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Increase clock frequency of application_fpga
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