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Swap roles of xtval and xtval2 #379
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I agree this is more consistent. I do wonder if we want to allocate more values in *cause instead of adding all the *tval2 registers or if that is a more contentious change.
Maybe allocating bits 24-31 of mcause for a "sub-cause" field could be easier since mcause >= 64 is reserved?
But regardless of whether we want to make that change I think this makes it more consistent with other exceptions so LGTM.
We considered this before, but didn't take that approach because it would consume too much space in *cause, and other places connected to it like medeleg. In future, we will probably need to remove the CHERI fault cause 28 and instead use the new software-check fault cause (see #60). IMHO, we should keep what we currently have in the spec (and this PR) and await feedback from the ARC. |
I agree with @andresag01 , I think it's better to keep what we have and all this area is subject to change by the ARC |
Signed-off-by: Tariq Kurd <[email protected]>
Signed-off-by: Andres Amaya Garcia <[email protected]>
Swap the roles of xtval and xtval2 such that xtval holds the address on a CHERI fault and xtval2 holds the extra CHERI cause and type information for the exception. The following also had to change along the way: * Update old references to xtval that must now point to xtval2 * Add `htval2` because otherwise we do not get any CHERI information in HS-mode * Adjust diagrams and descriptions for xtval and xtval2 This PR is a follow up to riscv#373 --------- Signed-off-by: Tariq Kurd <[email protected]> Signed-off-by: Andres Amaya Garcia <[email protected]> Co-authored-by: Tariq Kurd <[email protected]>
Swap the roles of xtval and xtval2 such that xtval holds the address on a CHERI fault and xtval2 holds the extra CHERI cause and type information for the exception. The following also had to change along the way:
htval2
because otherwise we do not get any CHERI information in HS-modeThis PR is a follow up to #373