Swap roles of xtval and xtval2 (riscv#379)

Swap the roles of xtval and xtval2 such that xtval holds the address on a CHERI fault and xtval2 holds the extra CHERI cause and type information for the exception. The following also had to change along the way: * Update old references to xtval that must now point to xtval2 * Add `htval2` because otherwise we do not get any CHERI information in HS-mode * Adjust diagrams and descriptions for xtval and xtval2 This PR is a follow up to riscv#373 --------- Signed-off-by: Tariq Kurd <[email protected]> Signed-off-by: Andres Amaya Garcia <[email protected]> Co-authored-by: Tariq Kurd <[email protected]>
tariqkurd-repo · Oct 9, 2024 · 2538c57 · 2538c57
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diff --git a/src/hypervisor-integration.adoc b/src/hypervisor-integration.adoc
@@ -54,12 +54,32 @@ The reset value is 0.
 === Hypervisor Trap Value Register (htval)
 
 The <<htval>> register operates as described in cite:[riscv-priv-spec].
-Additionally, <<htval>> may be written with the exception codes described in
-xref:mtval[xrefstyle=short] when a CHERI exception occurs.
+
+<<htval>> is updated following the same rules as <<mtval>> for CHERI exceptions
+which are taken in HS-mode.
 
 .Hypervisor trap value register
 include::img/htvalreg.edn[]
 
+[#htval2,reftext="htval2"]
+=== Hypervisor Trap Value Register 2 (htval2)
+
+The <<htval2>> register is an HSXLEN-bit read-write register, which is added as
+part of {cheri_base_ext_name} when the hypervisor extension is supported. Its
+CSR address is 0x64b.
+
+<<htval2>> is updated following the same rules as <<mtval2>> for CHERI exceptions
+which are taken in HS-mode.
+
+The fields are identical to <<mtval2>> for CHERI exceptions.
+
+NOTE: <<htval2>> is not a standard RISC-V CSR, but <<mtval2>>
+is.
+
+.Hypervisor trap value register 2
+[#hstval2-format]
+include::img/htval2reg.edn[]
+
 [#vsstatus,reftext="vsstatus"]
 === Virtual Supervisor Status Register (vsstatus)
 
@@ -167,28 +187,28 @@ include::img/vstdcreg.edn[]
 [#vstval,reftext="vstval"]
 === Virtual Supervisor Trap Value Register (vstval)
 
-The <<vstval>> register is an SXLEN-bit read-write register.
+The <<vstval>> register is a VSXLEN-bit read-write register.
 
-When a fault is taken into VS-mode <<vstval>> is updated as for <<stval>> for all CHERI exceptions.
+<<vstval>> is updated following the same rules as <<mtval>> for CHERI exceptions
+which are taken in VS-mode.
 
 .Virtual supervisor trap value register
 [#vstval-format]
 include::img/vstvalreg.edn[]
 
-
 [#vstval2,reftext="vstval2"]
 === Virtual Supervisor Trap Value Register 2 (vstval2)
 
-The <<vstval2>> register is a VSXLEN-bit read-write register.
-
-The CSR address is 0x24b.
+The <<vstval2>> register is a VSXLEN-bit read-write register, which is added as
+part of {cheri_base_ext_name} when the hypervisor extension is supported. Its
+CSR address is 0x24b.
 
-When a fault is taken into VS-mode <<vstval2>> is updated as for <<mtval2>> for all CHERI exceptions.
-It is set to zero in all other cases.
+<<vstval2>> is updated following the same rules as <<mtval2>> for CHERI exceptions
+which are taken in VS-mode.
 
-NOTE: This is not a standard RISC-V CSR, but <<mtval2>> is. 0x24b is the regular location for the CSR.
+The fields are identical to <<mtval2>> for CHERI exceptions.
 
-<<vstval2>> holds the same set of values that <<stval2>> can hold.
+NOTE: <<vstval2>> is not a standard RISC-V CSR, but <<mtval2>> is.
 
 .Virtual supervisor trap value register 2
 [#vstval2-format]

diff --git a/src/img/htval2reg.edn b/src/img/htval2reg.edn
@@ -0,0 +1,20 @@
+[bytefield]
+----
+(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
+(def row-height 40)
+(def row-header-fn nil)
+(def left-margin 100)
+(def right-margin 100)
+(def boxes-per-row 32)
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "" "" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "HSXLEN-1"])})
+
+(draw-box "Reserved"   {:span 12})
+(draw-box "TYPE"       {:span 4})
+(draw-box "Reserved"   {:span 12})
+(draw-box "CAUSE"      {:span 4})
+
+(draw-box "HSXLEN-20" {:span 12 :borders {}})
+(draw-box "4"        {:span 4 :borders {}})
+(draw-box "12"       {:span 12 :borders {}})
+(draw-box "4"        {:span 4 :borders {}})
+----
diff --git a/src/img/htvalreg.edn b/src/img/htvalreg.edn
@@ -1,16 +1,14 @@
 [bytefield]
 ----
-(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 21}])
-(def row-height 40 )
+(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
+(def row-height 40)
 (def row-header-fn nil)
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 32)
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "HSXLEN-1"])})
 
-(draw-box "HSXLEN-1" {:span 31 :text-anchor "start" :borders {}})
-(draw-box "0" {:borders {}})
-
-(draw-box "htval" {:font-size 20 :span 32})
+(draw-box "htval"   {:span 32})
 
 (draw-box "HSXLEN" {:span 32 :borders {}})
 ----
diff --git a/src/img/mtval2reg.edn b/src/img/mtval2reg.edn
@@ -6,9 +6,15 @@
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 32)
-(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])})
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "" "" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])})
 
-(draw-box "Addr"   {:span 32})
+(draw-box "Reserved"   {:span 12})
+(draw-box "TYPE"       {:span 4})
+(draw-box "Reserved"   {:span 12})
+(draw-box "CAUSE"      {:span 4})
 
-(draw-box "MXLEN" {:span 32 :borders {}})
+(draw-box "MXLEN-20" {:span 12 :borders {}})
+(draw-box "4"        {:span 4 :borders {}})
+(draw-box "12"       {:span 12 :borders {}})
+(draw-box "4"        {:span 4 :borders {}})
 ----
diff --git a/src/img/mtvalreg.edn b/src/img/mtvalreg.edn
@@ -6,15 +6,9 @@
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 32)
-(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "" "" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])})
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])})
 
-(draw-box "Reserved"   {:span 12})
-(draw-box "TYPE"       {:span 4})
-(draw-box "Reserved"   {:span 12})
-(draw-box "CAUSE"      {:span 4})
+(draw-box "mtval"   {:span 32})
 
-(draw-box "MXLEN-20" {:span 12 :borders {}})
-(draw-box "4"        {:span 4 :borders {}})
-(draw-box "12"       {:span 12 :borders {}})
-(draw-box "4"        {:span 4 :borders {}})
+(draw-box "MXLEN" {:span 32 :borders {}})
 ----
diff --git a/src/img/stval2reg.edn b/src/img/stval2reg.edn
@@ -6,9 +6,15 @@
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 32)
-(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "SXLEN-1"])})
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "" "" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "SXLEN-1"])})
 
-(draw-box "Addr"   {:span 32})
+(draw-box "Reserved"   {:span 12})
+(draw-box "TYPE"       {:span 4})
+(draw-box "Reserved"   {:span 12})
+(draw-box "CAUSE"      {:span 4})
 
-(draw-box "SXLEN" {:span 32 :borders {}})
+(draw-box "SXLEN-20" {:span 12 :borders {}})
+(draw-box "4"        {:span 4 :borders {}})
+(draw-box "12"       {:span 12 :borders {}})
+(draw-box "4"        {:span 4 :borders {}})
 ----
diff --git a/src/img/stvalreg.edn b/src/img/stvalreg.edn
@@ -6,15 +6,9 @@
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 32)
-(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "" "" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "SXLEN-1"])})
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "SXLEN-1"])})
 
-(draw-box "Reserved"   {:span 12})
-(draw-box "TYPE"       {:span 4})
-(draw-box "Reserved"   {:span 12})
-(draw-box "CAUSE"      {:span 4})
+(draw-box "stval"   {:span 32})
 
-(draw-box "SXLEN-20" {:span 12 :borders {}})
-(draw-box "4"        {:span 4 :borders {}})
-(draw-box "12"       {:span 12 :borders {}})
-(draw-box "4"        {:span 4 :borders {}})
+(draw-box "SXLEN" {:span 32 :borders {}})
 ----
diff --git a/src/img/vstval2reg.edn b/src/img/vstval2reg.edn
@@ -6,9 +6,15 @@
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 32)
-(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "VSXLEN-1"])})
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "" "" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "VSXLEN-1"])})
 
-(draw-box "Addr"   {:span 32})
+(draw-box "Reserved"   {:span 12})
+(draw-box "TYPE"       {:span 4})
+(draw-box "Reserved"   {:span 12})
+(draw-box "CAUSE"      {:span 4})
 
-(draw-box "VSXLEN" {:span 32 :borders {}})
+(draw-box "VSXLEN-20" {:span 12 :borders {}})
+(draw-box "4"         {:span 4 :borders {}})
+(draw-box "12"        {:span 12 :borders {}})
+(draw-box "4"         {:span 4 :borders {}})
 ----
diff --git a/src/img/vstvalreg.edn b/src/img/vstvalreg.edn
@@ -6,15 +6,9 @@
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 32)
-(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "" "" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "VSXLEN-1"])})
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "VSXLEN-1"])})
 
-(draw-box "Reserved"   {:span 12})
-(draw-box "TYPE"       {:span 4})
-(draw-box "Reserved"   {:span 12})
-(draw-box "CAUSE"      {:span 4})
+(draw-box "vstval"   {:span 32})
 
-(draw-box "VSXLEN-20" {:span 12 :borders {}})
-(draw-box "4"         {:span 4 :borders {}})
-(draw-box "12"        {:span 12 :borders {}})
-(draw-box "4"         {:span 4 :borders {}})
+(draw-box "VSXLEN" {:span 32 :borders {}})
 ----
diff --git a/src/insns/atomic_exceptions.adoc b/src/insns/atomic_exceptions.adoc
@@ -20,7 +20,7 @@ All misaligned atomics cause a store/AMO address misaligned exception to allow s
 +
 When these instructions cause CHERI exceptions, _CHERI data fault_
 is reported in the TYPE field and the following codes may be
-reported in the CAUSE field of <<mtval>> or <<stval>>:
+reported in the CAUSE field of <<mtval2>> or <<stval2>>:
 
 <<<
 

diff --git a/src/insns/cbo_exceptions.adoc b/src/insns/cbo_exceptions.adoc
@@ -1,7 +1,7 @@
 Exceptions::
 CHERI fault exceptions when the authorising capability fails one of the checks
-listed below; in this case, _CHERI data fault_ is reported in the <<mtval>> or
-<<stval>> TYPE field and the corresponding code is written to CAUSE.
+listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
+<<stval2>> TYPE field and the corresponding code is written to CAUSE.
 +
 ifdef::cbo_inval[]
 The CBIE bit in <<menvcfg>> and <<senvcfg>> indicates whether

diff --git a/src/insns/condbr_common.adoc b/src/insns/condbr_common.adoc
@@ -2,4 +2,4 @@ Exceptions::
 When the target address is not within the <<pcc>>'s bounds, and the branch is taken,
 a _CHERI jump or
 branch fault_ is reported in the TYPE field and Bounds violation is reported in
-the CAUSE field of <<mtval>> or <<stval>>:
+the CAUSE field of <<mtval2>> or <<stval2>>:
diff --git a/src/insns/hypv-virt-loadx.adoc b/src/insns/hypv-virt-loadx.adoc
@@ -42,8 +42,8 @@ to `rd`.
 
 Exceptions::
 CHERI fault exception when the authorising capability fails one of the checks
-listed below; in this case, _CHERI data fault_ is reported in the <<mtval>> or
-<<stval>> TYPE field and the corresponding code is written to CAUSE.
+listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
+<<stval2>> TYPE field and the corresponding code is written to CAUSE.
 +
 [%autowidth,options=header,align=center]
 |==============================================================================

diff --git a/src/insns/jalr_32bit.adoc b/src/insns/jalr_32bit.adoc
@@ -44,7 +44,7 @@ instruction following the jump is written to `rd`.
 Exceptions::
 When these instructions cause CHERI exceptions, _CHERI jump or branch fault_
 is reported in the TYPE field and the following codes may be
-reported in the CAUSE field of <<mtval>> or <<stval>>:
+reported in the CAUSE field of <<mtval2>> or <<stval2>>:
 
 [%autowidth,options=header,align=center]
 |==============================================================================

diff --git a/src/insns/load_exceptions.adoc b/src/insns/load_exceptions.adoc
@@ -9,8 +9,8 @@ to CLEN/8.
 +
 endif::[]
 CHERI fault exception when the authorising capability fails one of the checks
-listed below; in this case, _CHERI data fault_ is reported in the <<mtval>> or
-<<stval>> TYPE field and the corresponding code is written to CAUSE.
+listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
+<<stval2>> TYPE field and the corresponding code is written to CAUSE.
 +
 [%autowidth,options=header,align=center]
 |==============================================================================

diff --git a/src/insns/store_exceptions.adoc b/src/insns/store_exceptions.adoc
@@ -9,8 +9,8 @@ to CLEN/8.
 +
 endif::[]
 CHERI fault exception when the authorising capability fails one of the checks
-listed below; in this case, _CHERI data fault_ is reported in the <<mtval>> or
-<<stval>> TYPE field and the corresponding code is written to CAUSE.
+listed below; in this case, _CHERI data fault_ is reported in the <<mtval2>> or
+<<stval2>> TYPE field and the corresponding code is written to CAUSE.
 +
 [%autowidth,options=header,align=center]
 |==============================================================================

diff --git a/src/insns/zcmt_cmjalt.adoc b/src/insns/zcmt_cmjalt.adoc
@@ -41,7 +41,7 @@ Requires <<jvtc>> to be tagged, not sealed, have <<x_perm>> and for the full XLE
 {cheri_cap_mode_name} Exceptions::
 When these instructions cause CHERI exceptions, _CHERI instruction fetch fault_
 is reported in the TYPE field and the following codes may be
-reported in the CAUSE field of <<mtval>> or <<stval>>:
+reported in the CAUSE field of <<mtval2>> or <<stval2>>:
 
 [width="50%",options=header,cols="2,^1",align=center]
 |==============================================================================

diff --git a/src/insns/zcmt_cmjt.adoc b/src/insns/zcmt_cmjt.adoc
@@ -41,7 +41,7 @@ Requires <<jvtc>> to be tagged, not sealed, have <<x_perm>> and for the full XLE
 {cheri_cap_mode_name} Exceptions::
 When these instructions cause CHERI exceptions, _CHERI instruction fetch fault_
 is reported in the TYPE field and the following codes may be
-reported in the CAUSE field of <<mtval>> or <<stval>>:
+reported in the CAUSE field of <<mtval2>> or <<stval2>>:
 
 [width="50%",options=header,cols="2,^1",align=center]
 |==============================================================================