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MarwanEid1/README.md

Hi there

  • For my graduation project, I worked on UVM-Based Functional Verification of PCIe PHY Layer
  • I’m currently learning Digital Design and Functional Verification
  • How to reach me: [email protected]
  • Skills & Tools:
    • Design: FPGA Flow and Architecture - ASIC Flow and Architecture - Combinational and Sequential Logic - FSMs - SystemVerilog - Verilog - VHDL - Hierarchical Design - Synthesis - STA - CDC - Physical Design
    • Verification Basics: Testing Concepts - Verification Flow - Verification Planning
    • SystemVerilog: Data Types - Process Blocks - Hierarchical Structures - Compiler Directives - Scheduling Semantics - Assignments - Classes - OOP - Randomization - Coverage - SVA
    • UVM: Phasing - Base Classes - Factory - Resources, Configurations - TLM - Sequences, Sequencers - Drivers, Monitors - Components - Full Environment
    • EDA Tools: Synopsys (VCS, Design Compiler, IC Compiler, IC Compiler II, PrimeTime) - Mentor (QuestaSim) - Xilinx (Vivado, ISE) - Cadence (Virtuoso)
    • Programming & Scripting: MATLAB - Python - C/C++ - Tcl - OOP

Popular repositories Loading

  1. UVM-Scrambler UVM-Scrambler Public

    Functional verification of BB scrambler IP in SystemVerilog using Mentor QuestaSim.

    SystemVerilog 1

  2. UVM-SPRAM UVM-SPRAM Public

    Digital design and UVM-based functional verification for single-port RAM in SystemVerilog using Mentor QuestaSim.

    SystemVerilog

  3. MarwanEid1 MarwanEid1 Public

    About me

  4. 2D-Parametric-Systolic-Array 2D-Parametric-Systolic-Array Public

    Digital design and verification of parametric n × n systolic array for matrix multiplication in SystemVerilog using Xilinx Vivado and Mentor QuestaSim.

    SystemVerilog 1

  5. UART-Design UART-Design Public

    Digital design and verification of a full-duplex 8-bit UART protocol with support for parity bit and error flags in SystemVerilog using Xilinx Vivado and Mentor QuestaSim.

    SystemVerilog