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tscheipel/README.md

Hi there 👋

  • 🚀 I'm a Postdoctoral researcher and teacher at the Embedded Architectures & Systems Group, Graz University of Technology.
  • 🌟 Specializing in flexible and runtime-reconfigurable FPGA-based microcontroller architectures for embedded systems based on RISC-V.
  • 🔧 Building innovative solutions in research and teaching for dynamic and reconfigurable embedded systems.
  • 📚 Advocating for Open Educational Resources (OER) to make knowledge accessible and foster collaborative learning.

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  1. HaDes-V HaDes-V Public template

    HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU G…

    SystemVerilog 29 1