sgherbst / svreal Star 41 Code Issues Pull requests Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim Updated Jan 13, 2021 SystemVerilog
kaushalmodi / custom_uvm_report_server Star 34 Code Issues Pull requests Customized UVM Report Server vcs systemverilog synopsys uvm cadence xcelium Updated Feb 10, 2020 SystemVerilog
prernamittal / VerilogAlarmClock Star 0 Code Issues Pull requests This project implements a digital clock with alarm functionality in Verilog and SystemVerilog. verilog systemverilog xcelium Updated Jun 26, 2023 SystemVerilog