Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)
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Updated
May 26, 2024 - C
Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
This Repository shows the implementation and results of various codes that I write in Verilog HDL
simple system verilog example using an LFSR as the application
Verilog_Compiler is now available in GitHub Marketplace! This tool can quickly compile Verilog code and check for errors, making it an essential tool for developers.
Exemplos feito em verilog para estudos
Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL
my library of different digital hardware circuit designs and logic
This is a repository containing my solutions to the problem statements given on HDLBits website.
Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
Repo of my HDL exercises
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…
سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
2-Term Karatsuba and 3-Term Karatsuba Algorithm on FPGAs in Vivado using Verilog with diffrent bits and with 3 diffrent method.
This project is done in Vivado in Verilog with hardware implementation and the project is optimized Schoolbook multiplier which is much faster than the traditional ones
Traffic Light Controller using Verilog done in Vivado
100 Days challenge to improve digital desinging using languages like Verilog & SystemVerilog
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
This is a 4*4 Array_Multiplier_project using Verilog HDL. This is successfully implemented on FPGA board.
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