Open Source Verilog Modules
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Updated
Jan 25, 2023 - Verilog
Open Source Verilog Modules
This project is to design a processor and memory in the digital system design course at university.
The asynchronous interface is spercifically designed for scalable parallel datapaths.
Risc-V 32i processor written in the Verilog HDL
👾 My studies with Verilog and notions of digital systems.
Se hace una recopilación de los sensores utilizados para el proyecto de una casa domotica. Compilado en ISE Design 14.6 y Simulado en ISim.
My ongoing practice verilog hdl codes.
A dump for my VHDL projects, because I want to have a better understanding of Verilog and also Logic circuits.
Simple example programs for the Lattice iCEblink40-HX1K Evaluation Kit in Verilog for fun and learning.
Digital System Design Verilog Implementation
This project is done in Vivado in Verilog with hardware implementation and the project is optimized Schoolbook multiplier which is much faster than the traditional ones
Verilog programs in gate level, dataflow & behavioural modelling with testbenches written in intel FPGA tested with ModelSim simulator
A small CPU / ISA and a testbench that displays its instructions' equivalent in assembly&machine language.
32-bits MIPS Processor with 5-stage pipeline
سورس کد پروژه های درس طراحی سیستم های دیجیتال برنامه پذیر دانشگاه تبریز مقطع کارشناسی رشته مهندسی کامپیوتر
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