VHDL 2008/93/87 simulator

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

VUnit is a unit testing framework for VHDL/SystemVerilog

OpenADR-PenTest-Lab is a testbed for learning web app penetration testing in Open Automated Demand Response (OpenADR) systems. It provides a realistic environment for security enthusiasts to practice pen testing on a Virtual Top Node (VTN) server for demand response applications, grid-interactive efficient buildings (GEB), and OpenADR protocols.

AutoDRIVE-AVL DRIVINGCUBE Development & Integration

uvm framework generator

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

This repository contain basic verilog codes which include the implementation of DLD (digital logic desgin ) circuits.

System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool

UART Transmitter and Receiver implementation for FPGA

AutoDRIVE-AVL DRIVINGCUBE Development & Integration

UVM Command Center - UVM Testbench Builder (DEMO) - Demo of UVM Verification Workflow IDE.

Generates verilogA testbench (stimulus and waveforms) for verification of analog IPs (VLSI design)

"Repository containing a collection of Verilog code modules and test bench for digital design projects. "

Generate the uvm testbench automatically