AI acceleration using matrix multiplication with half the multiplications
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Updated
Mar 28, 2024 - Python
AI acceleration using matrix multiplication with half the multiplications
AutoSA: Polyhedral-Based Systolic Array Compiler
Research and Materials on Hardware implementation of Transformer Model
A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
A general framework for optimizing DNN dataflow on systolic array
Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
Systolic-array based Deep Learning Accelerator generator
Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.
Template for project1 TPU
EE599 Accelerated Computing on FPGA
Systolic arrays graphical simulator (SAGS), written in Python.
A general framework for optimizing DNN dataflow on systolic array
SystemVerilog module for matrix multiplication
In this repository you can find all of my projects for Parallel Processing Course when I was in 2nd semester of my master's at SUT.
This is an unfinished test model of CNN, based on cnn.h5 Keras pretrained model EN10/KerasMNIST@4ef71d6/cnn.h5 .
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
SPICE and Behavioral simulation of systolic array equipped with error detection ABFT
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