byuccl / spydrnet Star 85 Code Issues Pull requests A flexible framework for analyzing and transforming FPGA netlists. Official repository. fpga digital hardware transformations eda circuits cad circuit hardware-designs transformation circuit-analysis netlist computer-aided-design fpgas netlist-parser circuit-design electronic-design-automation netlists edif Updated Mar 4, 2024 Python
najaeda / naja-verilog Star 21 Code Issues Pull requests A standalone structural (gate-level) verilog parser parser cpp eda verilog netlist semiconductor netlist-parser electronic-design-automation Updated Apr 2, 2024 C++
arasgungore / netlist-solver Star 19 Code Issues Pull requests A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit. algorithm algorithms matlab circuit-simulator circuits circuit circuit-simulation nodal-analysis circuit-analysis netlist mna circuits-simulator analog-design netlist-parser netlists circuit-theory modified-node-analysis modified-nodal-analysis node-analysis netlist-simulator Updated Aug 8, 2022 MATLAB
gabrielseibel1 / BINS Star 1 Code Issues Pull requests BINS Is Not SPICE: a SPICE-inspired circuit simulator. circuit-simulator spice netlist-parser Updated Jul 14, 2018 C++