Intermediate Language (IL) for Hardware Accelerator Generators
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Updated
Jun 5, 2024 - Rust
Intermediate Language (IL) for Hardware Accelerator Generators
learn the combinational and sequential logic circuit.
Projects showcase
Wa'el Engineering Project Repository
HeteroCL-MLIR dialect for accelerator design
Calender Implementation using VHDL on FPGA Board
Allo: A Programming Model for Composable Accelerator Design
A collection of notes, summaries, and projects based on the book "FPGA Programming for Beginners" by Frank Bruno.
The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.
Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation.
learning about FPGA
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Set of examples written for hardware acceleration via TornadoVM
Proyecto de Tesis donde se realiza procesamiento digital de audio para hacer una pedalera de efectos de guitarra con la FPGA DE10-Lite
Object oriented, templated building blocks that should be able to run on an fpga. A standard interface for integrating system on chip (SOC).
Simple implementation of PCIE4C-based pcie transfer on Xilinx Ultrascale+ FPGAs
During the EL-203 course, we had to make a elevator controller project under Professor Biswajit Mishra.
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
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