VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design
-
Updated
Oct 18, 2023 - VHDL
VHDL implementations of half-adders, full-adders, and a 4-bit adder for digital circuit design
Codes written by me in my Digital Logic Design course.
This repository contains the project files and report for an ASCII letter to Morse Code converter built using only basic sequential and combinational logic circuits.
This repository contains synthesizable VHDL code for basic combinational logic circuits such as Adder with register, 2:4 decoder, 4:2 priority encoder, Multiplier with register and other circuits.
MUX VHDL | Układ kombinacyjny VHDL
Circuito combinacional con entrada de 4 bits (número sin signo en binario puro) y salida con un número de 4 bits, su valor es redondear la operación 4 x RAIZ CUADRADA(y) al entero más próximo. El circuito se diseña de diversas maneras, cada una con una descripción en VHDL como arquitectura de la entidad.
Repository for chip documentation (CS220 SP 2018)
This project contains Java code to implement a Kmap solver, limited to 3 variables. On entering the truth table or minterms, it gives the minimal SOP form, using 3-variable K-map as the minimization technqiue.
This script lists out all paths from inputs to outputs of an input combinational circuit in the form of structural/gate-level modelling in verilog. The BFS graph algorithm is used.
Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.
Design of the implementation of a calculator connected on the integrated FPGA
Source code for various Verilog-based projects and assignments
These are the assignments of Second year Analog Digital Electronicd subject
This Repo Contains Projects implemented for this Course:)
An efficient combinatorics library for JavaScript to generate and get the list of all Permutations and Combinations with the ability to enable or disable repetition. (utilizing ES2015 generators)
This is a Combinational Circuit Logic Simulation Tool. There is a C++ version and a C version.
A 32-bit ALU using combinational logic written in Verilog.
Basic tools, methods and procedures to design combinational and sequential digital circuits and systems. Topics include number systems, Boolean algebra, logic minimization, circuit design, memory elements, and finite state machine design.
simulation of essential combinational logic circuits with boolean algebra
Add a description, image, and links to the combinational-logic topic page so that developers can more easily learn about it.
To associate your repository with the combinational-logic topic, visit your repo's landing page and select "manage topics."