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istyle-verilog-formatter
istyle-verilog-formatter PublicOpen source implementation of a Verilog formatter
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eecs_301_reference_designs_2015_spring
eecs_301_reference_designs_2015_spring PublicReference designs for CWRU EECS 301 labs assigned Spring 2015
Verilog 1
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EECS_301_Labs
EECS_301_Labs PublicEECS 301 Spring 2014 Projects: Thomas Murphy and Camille Jackman
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