i-2DDCT_CTRL mvd in i-2DDCT, core corner cases fix

i-2DDCT_CTRL emebedded in i-2DDCT core and port fixed User space (TOP_LEVEL_TB) input process fixed added Voltage Trace ROM and INT_EMU from norm in testbench corener cases of i-2DDCT core fixed around halting in 7th,0th input data -> ROMx_DOUT were desynchronized with respect to pipeline, a latch is used to fix this desynch.
simoneruffini · Sep 9, 2021 · 5803333 · 5803333
1 parent af6d3fd
commit 5803333
Show file tree

Hide file tree

Showing 10 changed files with 753 additions and 156 deletions.
diff --git a/hdl/I_DCT1S.vhd b/hdl/I_DCT1S.vhd
@@ -132,6 +132,9 @@ architecture BEHAVIORAL of I_DCT1S is
  signal block_cmplt_s_d : std_logic_vector(C_PIPELINE_STAGES - 1 downto 0);
  signal odv_gate : std_logic; -- Halt all idct delay
 
+ signal romx_dout_latch_en_n : std_logic;
+ signal rome_dout_latch : rom1_data_t;
+ signal romo_dout_latch : rom1_data_t;
  signal rome_dout_d1 : rom1_data_t;
  signal romo_dout_d1 : rom1_data_t;
  signal rome_dout_d2 : rom1_data_t;
@@ -595,6 +598,11 @@ begin
 
  end process P_DATA_BUF_AND_CTRL;
 
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ -- Output Data Valid gate
+ --
+ -- Used to corectly send data (enable ODV) to the user space (debug)
+
  P_ODV_GATE : process (CLK, RST) is
  begin
 
@@ -672,6 +680,43 @@ begin
 
  end process P_DELAYS;
 
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ -- ROMx_DOUT latch
+ -- 
+ -- This latch is used when the system halts. In this period the expected
+ -- behavior is that ROMx_DOUT doesn't change, this does not happen because 
+ -- ROMx_ADDR did, hence this latch is used to keep the value stable when system 
+ -- restarts.
+ -- Processes that read ROMx_DOUT need to use the latched value when the system
+ -- restarts and a new value was written (romx_dout_latch_en_n = '1')
+
+ P_ROMX_DOUT_LATCH: process(CLK,RST) is
+ begin
+ if(RST = '1') then
+ romx_dout_latch_en_n <= '0';
+ elsif(rising_edge(CLK)) then
+ if (i_dct_halt = '1') then
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ -- HALTED EXECUTION
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ if(romx_dout_latch_en_n = '0') then
+ rome_dout_latch<= ROME_DOUT;
+ romo_dout_latch<= ROMO_DOUT;
+ romx_dout_latch_en_n <= '1';
+ end if;
+ else
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ -- NORMAL EXECUTION
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ -- Disable latch after the system is no more halted
+ if(romx_dout_latch_en_n = '1') then
+ romx_dout_latch_en_n <= '0';
+ end if;
+
+ end if;
+ end if;
+ end process P_ROMX_DOUT_LATCH;
+
  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  -- Data Pipeline
 
@@ -706,6 +751,23 @@ begin
  (resize(signed(ROMO_DOUT(2)), C_PL1_DATA_W - 2) & "00"),
  C_PL1_DATA_W));
  end if;
+
+ if (romx_dout_latch_en_n = '1') then
+ if (is_even = '1') then
+ dcto_1 <= std_logic_vector(resize
+ (resize(signed(rome_dout_latch(0)), C_PL1_DATA_W) +
+ (resize(signed(rome_dout_latch(1)), C_PL1_DATA_W - 1) & '0') +
+ (resize(signed(rome_dout_latch(2)), C_PL1_DATA_W - 2) & "00"),
+ C_PL1_DATA_W));
+ else
+ dcto_1 <= std_logic_vector(resize
+ (resize(signed(romo_dout_latch(0)), C_PL1_DATA_W) +
+ (resize(signed(romo_dout_latch(1)), C_PL1_DATA_W - 1) & '0') +
+ (resize(signed(romo_dout_latch(2)), C_PL1_DATA_W - 2) & "00"),
+ C_PL1_DATA_W));
+ end if;
+ end if;
+
  if (is_even_d(1 - 1) = '1') then -- is even 1 clk delay
  dcto_2 <= std_logic_vector(resize
  (signed(dcto_1) +
@@ -814,6 +876,10 @@ begin
 
  rome_dout_d1 <= ROME_DOUT;
  romo_dout_d1 <= ROMO_DOUT;
+ if (romx_dout_latch_en_n = '1') then
+ rome_dout_d1 <= rome_dout_latch;
+ romo_dout_d1 <= romo_dout_latch;
+ end if;
  rome_dout_d2 <= rome_dout_d1;
  romo_dout_d2 <= romo_dout_d1;
  rome_dout_d3 <= rome_dout_d2;

diff --git a/hdl/I_DCT2S.vhd b/hdl/I_DCT2S.vhd
@@ -131,6 +131,9 @@ architecture BEHAVIORAL of I_DCT2S is
  signal odv_s : std_logic;
  signal odv_d : std_logic_vector(C_PIPELINE_STAGES - 1 downto 0);
 
+ signal romx_dout_latch_en_n : std_logic;
+ signal rome_dout_latch : rom2_data_t;
+ signal romo_dout_latch : rom2_data_t;
  signal rome_dout_d1 : rom2_data_t;
  signal romo_dout_d1 : rom2_data_t;
  signal rome_dout_d2 : rom2_data_t;
@@ -431,7 +434,7 @@ begin
  ram_row_from_ram_d1 <= '0';
 
  last_dbuf_cmplt_latch <= '0';
- DATA_READY_ACK <= '0';
+ DATA_READY_ACK  <= '0';
  elsif (CLK='1' and CLK'event) then
  -- Global Defaults
  pull_chkpnt_ram_cmplt <= '0';
@@ -554,19 +557,18 @@ begin
  if (ram_col2 = N - 2) then
  ram_row <= ram_row + 1;
 
- if(ram_row2 = N - 1) then
+ if (ram_row2 = N - 1) then
  BLOCK_CMPLT <= '1';
  end if;
  end if;
 
-
  -- A line was read now it goes into the pipeline
  if (ram_col2 = N - 1) then
  ram_row2 <= ram_row2 + 1;
 
  if (ram_row2 = N - 1) then
- stage1_en  <= '0';
- ram_col  <= (others => '0');
+ stage1_en <= '0';
+ ram_col <= (others => '0');
  end if;
 
  -- after this sum dbuf is in range of -256 to 254 (min to max)
@@ -639,6 +641,11 @@ begin
 
  end process P_DATA_BUF_AND_CTRL;
 
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ -- Output Data Valid gate
+ --
+ -- Used to corectly send data (enable ODV) to the user space
+
  P_ODV_GATE : process (CLK, RST) is
  begin
 
@@ -707,6 +714,44 @@ begin
 
  end process P_DELAYS;
 
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ -- ROMx_DOUT latch
+ --
+ -- This latch is used when the system halts. In this period the expected
+ -- behavior is that ROMx_DOUT doesn't change, this does not happen because
+ -- ROMx_ADDR did, hence this latch is used to keep the value stable when system
+ -- restarts.
+ -- Processes that read ROMx_DOUT need to use the latched value when the system
+ -- restarts and a new value was written (romx_dout_latch_en_n = '1')
+
+ P_ROMX_DOUT_LATCH : process (CLK, RST) is
+ begin
+
+ if (RST = '1') then
+ romx_dout_latch_en_n <= '0';
+ elsif (CLK'event and CLK = '1') then
+ if (i_dct_halt = '1') then
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ -- HALTED EXECUTION
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ if (romx_dout_latch_en_n = '0') then
+ rome_dout_latch <= ROME_DOUT;
+ romo_dout_latch <= ROMO_DOUT;
+ romx_dout_latch_en_n <= '1';
+ end if;
+ else
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ -- NORMAL EXECUTION
+ --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ -- Disable latch after the system is no more halted
+ if (romx_dout_latch_en_n = '1') then
+ romx_dout_latch_en_n <= '0';
+ end if;
+ end if;
+ end if;
+
+ end process P_ROMX_DOUT_LATCH;
+
  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  -- Data Pipeline
 
@@ -741,6 +786,21 @@ begin
  (resize(signed(ROMO_DOUT(2)), C_PL2_DATA_W - 2) & "00"),
  C_PL2_DATA_W));
  end if;
+ if (romx_dout_latch_en_n = '1') then
+ if (is_even = '1') then
+ dcto_1 <= std_logic_vector(resize
+ (resize(signed(rome_dout_latch(0)), C_PL2_DATA_W) +
+ (resize(signed(rome_dout_latch(1)), C_PL2_DATA_W - 1) & '0') +
+ (resize(signed(rome_dout_latch(2)), C_PL2_DATA_W - 2) & "00"),
+ C_PL2_DATA_W));
+ else
+ dcto_1 <= std_logic_vector(resize
+ (resize(signed(romo_dout_latch(0)), C_PL2_DATA_W) +
+ (resize(signed(romo_dout_latch(1)), C_PL2_DATA_W - 1) & '0') +
+ (resize(signed(romo_dout_latch(2)), C_PL2_DATA_W - 2) & "00"),
+ C_PL2_DATA_W));
+ end if;
+ end if;
 
  if (is_even_d(C_PIPELINE_STAGES - C_PIPELINE_STAGES) = '1') then -- is even 1 clock delay
  dcto_2 <= std_logic_vector(resize
@@ -866,6 +926,10 @@ begin
  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  rome_dout_d1 <= ROME_DOUT;
  romo_dout_d1 <= ROMO_DOUT;
+ if (romx_dout_latch_en_n = '1') then
+ rome_dout_d1 <= rome_dout_latch;
+ romo_dout_d1 <= romo_dout_latch;
+ end if;
  rome_dout_d2 <= rome_dout_d1;
  romo_dout_d2 <= romo_dout_d1;
  rome_dout_d3 <= rome_dout_d2;

diff --git a/hdl/NORM b/hdl/NORM
diff --git a/hdl/VTRACE_ROM.vhd b/hdl/VTRACE_ROM.vhd
@@ -0,0 +1,104 @@
+--------------------------------------------------------------------------------
+-- Engineer: Simone Ruffini [[email protected]]
+--
+-- Create Date: Mon Sep 6 17:13:25 CEST 2021
+-- Design Name: VTRACE_ROM
+-- Module Name: VTRACE_ROM.vhd - Behavioral
+-- Project Name: i-2DDCT
+-- Description: Voltage Trace ROM for INT_EMU
+--
+-- Revision:
+-- Revision 00 - Simone Ruffini
+-- * File created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+
+----------------------------- PACKAGES/LIBRARIES -------------------------------
+
+library IEEE;
+ use IEEE.STD_LOGIC_1164.all;
+ use IEEE.NUMERIC_STD.all;
+ use IEEE.MATH_REAL.all;
+
+----------------------------- ENTITY -------------------------------------------
+
+entity VTRACE_ROM is
+ generic (
+ NUM_ELEMENTS_ROM : integer
+ );
+ port (
+ CLK : in std_logic;
+ RADDR : in natural range 0 to NUM_ELEMENTS_ROM - 1;
+ DOUT : out integer
+ );
+end entity VTRACE_ROM;
+
+----------------------------- ARCHITECTURE -------------------------------------
+
+architecture BEHAVIORAL of VTRACE_ROM is
+
+ --########################### CONSTANTS 1 ####################################
+ constant C_MAX_VOLTAGE : real := 3.3;
+ constant C_START_DISCHARGE : real := 0.2;
+
+ constant C_TRACE_DURATION : natural := 5;
+
+ constant C_STEP : real := real(C_TRACE_DURATION) / real(NUM_ELEMENTS_ROM);
+
+ --########################### TYPES ##########################################
+
+ type rom_t is array (0 to NUM_ELEMENTS_ROM - 1) of integer;
+
+ --########################### FUNCTIONS ######################################
+
+ function trace_function (x : real) return real is
+ begin
+
+ if (x < C_START_DISCHARGE) then
+ return C_MAX_VOLTAGE;
+ elsif (x >= C_START_DISCHARGE AND x < (C_START_DISCHARGE + 1.0)) then
+ return C_MAX_VOLTAGE * EXP(-x + C_START_DISCHARGE);
+ else
+ return C_MAX_VOLTAGE * (1.0 - EXP(-x + (C_START_DISCHARGE + 0.5)));
+ end if;
+
+ end function;
+
+ impure function generate_trace return rom_t is
+ variable vtrace_rom : rom_t;
+ begin
+ for i in 0 to NUM_ELEMENTS_ROM - 1 loop
+ vtrace_rom(i) := integer(ceil(1000.0 * trace_function(C_STEP * i)));
+ end loop;
+ return vtrace_rom;
+ end function;
+
+ --########################### CONSTANTS 2 ####################################
+
+ --########################### SIGNALS ########################################
+
+ signal rom : rom_t := generate_trace;
+
+ --########################### ARCHITECTURE BEGIN #############################
+
+begin
+
+ --########################### ENTITY DEFINITION ##############################
+
+ --########################## OUTPUT PORTS WIRING #############################
+
+ --########################## COBINATORIAL FUNCTIONS ##########################
+
+ --########################## PROCESSES #######################################
+
+ P_OUTPUT : process (clk) is
+ begin
+
+ if (clk'event and clk = '1') then
+ DOUT <= rom(RADDR); --get the address read it as unsigned and convert to integer to get the value from ROM(integer)
+ end if;
+
+ end process P_OUTPUT;
+
+end architecture BEHAVIORAL;