Trying to learn Wishbone by implementing few master/slave devices
a slave device does nothing - it only responds with an ACK as soon as possible
a master device does nothing - it basically only starts a bus cycle, waits for ACK and that's it
a slave device which implements a set of basic registers - writing to them will retain the given value, and reading will return it.
number of registers is configurable and is done via a module parameter
this master device continuously issues SINGLE WRITE and then SINGLE READ bus cycles over a range of memory address space (configurable via module parameters)
a simple round robin interconnect, supporting multiple masters and multiple slave devices
a simple device which has both a master and a slave interface, which means it can be loopbacked