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Merge pull request #36 from saursin/refactor-rtl
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Refactor RTL
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@saursin
saursin authored Feb 21, 2022
2 parents 86a3992 + 00ea4f5 commit 3b75d05
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Showing 28 changed files with 1,602 additions and 1,182 deletions.
26 changes: 22 additions & 4 deletions Makefile
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Expand Up @@ -61,19 +61,38 @@ Target = atombones
VC = verilator
VFLAGS = -cc -Wall --relative-includes --trace -D__ATOMSIM_SIMULATION__

verilog_files = $(rtl_dir)/Timescale.vh
verilog_files += $(rtl_dir)/core/Utils.vh
verilog_files += $(rtl_dir)/core/Defs.vh
verilog_files += $(rtl_dir)/core/AtomRV.v
verilog_files += $(rtl_dir)/core/Alu.v
verilog_files += $(rtl_dir)/core/Decode.v
verilog_files += $(rtl_dir)/core/RegisterFile.v
verilog_files += $(rtl_dir)/core/CSR_Unit.v

# Target Specific definitions
ifeq ($(Target), atombones) # ----- AtomBones -----
verilog_topmodule = AtomBones
verilog_topmodule_file = $(rtl_dir)/$(verilog_topmodule).v
verilog_files = $(verilog_topmodule_file) $(rtl_dir)/Timescale.vh $(rtl_dir)/Config.vh $(rtl_dir)/core/AtomRV.v $(rtl_dir)/core/Alu.v $(rtl_dir)/core/Decode.v $(rtl_dir)/core/RegisterFile.v $(rtl_dir)/core/CSR_Unit.v
verilog_files += $(verilog_topmodule_file)

sim_cpp_backend = $(sim_dir)/Backend_AtomBones.hpp
CFLAGS += -DTARGET_ATOMBONES
else
ifeq ($(Target), hydrogensoc) # ----- HydrogenSoC -----
verilog_topmodule = HydrogenSoC
verilog_topmodule_file = $(rtl_dir)/$(verilog_topmodule).v
verilog_files = $(verilog_topmodule_file) $(rtl_dir)/Timescale.vh $(rtl_dir)/Config.vh $(rtl_dir)/uncore/BiDirectionalIO.v $(rtl_dir)/uncore/GPIO.v $(rtl_dir)/uncore/DualPortRAM_wb.v $(rtl_dir)/uncore/SinglePortRAM_wb.v $(rtl_dir)/uncore/simpleuart_wb.v $(rtl_dir)/uncore/simpleuart.v $(rtl_dir)/core/AtomRV_wb.v $(rtl_dir)/core/AtomRV.v $(rtl_dir)/core/Alu.v $(rtl_dir)/core/Decode.v $(rtl_dir)/core/RegisterFile.v $(rtl_dir)/core/CSR_Unit.v

verilog_files += $(rtl_dir)/core/AtomRV_wb.v
verilog_files += $(rtl_dir)/uncore/BiDirectionalIO.v
verilog_files += $(rtl_dir)/uncore/GPIO.v
verilog_files += $(rtl_dir)/uncore/DualPortRAM_wb.v
verilog_files += $(rtl_dir)/uncore/SinglePortRAM_wb.v
verilog_files += $(rtl_dir)/uncore/simpleuart_wb.v
verilog_files += $(rtl_dir)/uncore/simpleuart.v
verilog_files += $(rtl_dir)/HydrogenSoC_Config.vh
verilog_files += $(verilog_topmodule_file)

VFLAGS += -D__IMEM_INIT_FILE__='"$(RVATOM)/$(init_dir)/code.hex"'
VFLAGS += -D__DMEM_INIT_FILE__='"$(RVATOM)/$(init_dir)/data.hex"'

Expand Down Expand Up @@ -230,6 +249,7 @@ libs: $(build_dir) $(bin_dir)
@echo "$(COLOR_GREEN)>> Compiling software libraries ...$(COLOR_NC)"
cd sw/lib && make Target=$(Target)


# ======== Documentation ========
#~ docs : Generate atomsim C++ source documentation
.PHONY: docs
Expand All @@ -245,8 +265,6 @@ pdf-docs: docs $(doc_dir) $(doxygen_doc_dir)
mv doc/doxygen/latex/refman.pdf doc/Atomsim_source_documentation.pdf




# ======== clean ========
#~ clean : Clean atomsim build files
.PHONY: clean
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5 changes: 4 additions & 1 deletion boards/spartan6-mini/spartan6-mini.xise
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Original file line number Diff line number Diff line change
Expand Up @@ -319,6 +319,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
Expand Down Expand Up @@ -359,11 +360,13 @@
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../rtl/Timescale.vh" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/Config.vh" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/HydrogenSoC_Config.vh" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core/AtomRV_wb.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core/AtomRV.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core/Defs.vh" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core/Decode.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core/RegisterFile.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core/Utils.vh" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core/Alu.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/core/CSR_Unit.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../rtl/uncore/DualPortRAM_wb.v" xil_pn:type="FILE_VERILOG"/>
Expand Down
2 changes: 1 addition & 1 deletion install-toolchain.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ TOOLCHAIN_CONFIG=--enable-multilib
BUILD_JOBS=4

# Toolchain install root directory (Note: Toolchain will be installed inside a folder named TOOLCHAIN_NAME in the TOOLCHAIN_ROOTPATH)
TOOLCHAIN_ROOTPATH=/home/frozenalpha/opt/riscv
TOOLCHAIN_ROOTPATH=/home/${user}/opt/riscv

#########################################################
# You sould not change anything below this
Expand Down
50 changes: 29 additions & 21 deletions rtl/AtomBones.v
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@@ -1,10 +1,18 @@
/**
* Barebones Atom
*/
///////////////////////////////////////////////////////////////////
// File : AtomBones.v
// Author : Saurabh Singh ([email protected])
// Description : AtomBones is a wrapper for AtomRV_wb, it is a
// stub SoC target for AtomSim, which uses software simulated
// memories and communication modules.
///////////////////////////////////////////////////////////////////

`include "Timescale.vh"
`include "Config.vh"
`include "AtomBones_Config.vh"

`include "core/AtomRV.v"

`default_nettype none

module AtomBones
(
input wire clk_i,
Expand All @@ -26,22 +34,22 @@
input wire dmem_ack_i // DMEM Ack signal
);

// Core
AtomRV atom_core
(
.clk_i (clk_i),
.rst_i (rst_i),
.imem_addr_o (imem_addr_o),
.imem_data_i (imem_data_i),
.imem_valid_o (imem_valid_o),
.imem_ack_i (imem_ack_i),
.dmem_addr_o (dmem_addr_o),
.dmem_data_i (dmem_data_i),
.dmem_data_o (dmem_data_o),
.dmem_sel_o (dmem_sel_o),
.dmem_we_o (dmem_we_o),
.dmem_valid_o (dmem_valid_o),
.dmem_ack_i (dmem_ack_i)
);
// Core
AtomRV atom_core
(
.clk_i (clk_i),
.rst_i (rst_i),
.imem_addr_o (imem_addr_o),
.imem_data_i (imem_data_i),
.imem_valid_o (imem_valid_o),
.imem_ack_i (imem_ack_i),
.dmem_addr_o (dmem_addr_o),
.dmem_data_i (dmem_data_i),
.dmem_data_o (dmem_data_o),
.dmem_sel_o (dmem_sel_o),
.dmem_we_o (dmem_we_o),
.dmem_valid_o (dmem_valid_o),
.dmem_ack_i (dmem_ack_i)
);

endmodule
24 changes: 24 additions & 0 deletions rtl/AtomBones_Config.vh
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Original file line number Diff line number Diff line change
@@ -0,0 +1,24 @@
`ifndef __HYDROGENSOC_CONFIG_VH__
`define __HYDROGENSOC_CONFIG_VH__

// Reset address
`define SOC_RESET_ADDRESS 32'h00000000

// Atombones doesn't need the following parameters since everything
// other that the core is software simulated

// SoC Peripherals

// IRAM
// `define IRAM_ADDR 32'h00000000 // 0 GB boundry
// `define IRAM_SIZE 32'h00008000 // 32 KB

// // RAM
// `define RAM_ADDR 32'h04000000 // 0.5 GB boundry
// `define RAM_SIZE 32'h00002000 // 8 KB

// // UART
// `define UART_ADDR 32'h08000000 // 1.0 GB boundry
// `define UART_SIZE 32'h00000008 // 8 bytes

`endif //__HYDROGENSOC_CONFIG_VH__
30 changes: 0 additions & 30 deletions rtl/Config.vh
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