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C program to simulate and understand a Von Neumann architecture CPU with 8 registers, 16 bits memory, condition flags and program counter register.

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CPU Simulator

Created a C program to simulate and understand a Von Neumann architecture CPU with 8 registers, 16 bits memory, condition flags and program counter register.

Implemented the fetch-decode-execute cycle for 19 instructions by using binary operations.

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C program to simulate and understand a Von Neumann architecture CPU with 8 registers, 16 bits memory, condition flags and program counter register.

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