Implement appropriate atomic_yield for Armv7+

[jserv]

Spin-wait often involves active sleep (better known as "pause"). x86
has a direct assembly instruction named "PAUSE" which has two roles:
one is to hint at the operating systme that it might be ready to be
swapped out, and the other is to create a small delay. That delay is
useful as backoff from attempting to capture spinlocks, which improves
the behavior of the system and allows more efficient lock acquisition.

However, the "yield" instruction is not a good fit because it is
effectively a nop on most Arm cores and does not cause enough delay to
help backoff. The "isb" instruction is a barrier that, especially
inside a loop, creates a small delay without consuming ALU resources.

[daanx]

Hi @jserv; thanks for looking into this. However, the isb synchronizes the instruction stream which seems actually quite heavyweight. On Aarch64 Linux, they use wef (link so I think we should keep using this for aarch64 ; We may want to add a sevl instruction before it though now that I look at it again.

That leaves regular ARM32, I guess if yield is not good enough, isb is acceptable ?