ADVANCED-VLSI-DESIGN---ECSE-6680

This ECSE 6680 GitHub repository documents the development of a 100-tap low-pass FIR filter and an advanced low-pass IIR filter using Matlab and Verilog. It includes not just source code but also analyses of Matlab's design role, Verilog structure, and architectural choices between pipelining and parallel processing, supported by industry tools. Hardware implementation details are recorded, showcasing metrics like area, frequency, and power, alongside a comprehensive analysis section capturing the comparative study between the IIR and FIR filters. It reflects on quantization impacts, stability considerations, and overflow management strategies, delivering a narrative that bridges theoretical understanding with practical application. Both the FIR and IIR filters aim for the same stringent performance criteria: a transition region tightly bound between 0.2π to 0.23π rad/sample and stopband attenuation notching above 80dB. The repository not only highlights the methodical design process and the Verilog structural nuances but also captures the subtle yet critical aspects of IIR filter design, such as coefficient quantization and the recursive nature of its architecture, which demand a meticulous balance between performance and stability.