Discussions

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  Welcome to OpenFPGA Discussions!

  tangxifan announced Sep 21, 2021 in Announcements

  

  

  

  

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  Generate fabric for all architectures

  Gurusatwik asked Apr 24, 2024 in Q&A · Unanswered

  

  

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  Manual modelsim compilation and simulation errors

  chaitalisathe asked Apr 11, 2024 in Q&A · Unanswered

  

  

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  Status of FPGA-SDC Support of --group_config_block

  tornupnegatives asked Mar 22, 2024 in Q&A · Unanswered

  

  

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  Interconnection of Circuit blocks

  Gurusatwik asked Feb 16, 2024 in Q&A · Unanswered

  

  

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  fabric bitstream

  YazanBaddour started Feb 1, 2024 in General

  

  

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  some questions about timing report

  Chris202305 asked Jan 26, 2024 in Q&A · Unanswered

  

  

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  FPGA simulation question

  chaitalisathe asked Jan 23, 2024 in Q&A · Unanswered

  

  

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  some error about the template architecture files

  Chris202305 asked Jan 17, 2024 in Q&A · Unanswered

  

  

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  error in simulation

  YazanBaddour started Jan 15, 2024 in General

  

  

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  Manual configuration of FPGA through bitstream {where both FPGA fabric and bitstream are generated using OpenFPGA tool}

  chaitalisathe asked Jan 8, 2024 in Q&A · Answered

  

  

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  FPGA programming question

  schaferben asked Jan 8, 2024 in Q&A · Unanswered

  

  

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  The issues encountered when synthesizing the Verilog generated by OpenFPGA in Quartus

  Chris202305 asked Nov 14, 2023 in Q&A · Unanswered

  

  

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  Fpga fabric behavioral simulation

  YazanBaddour asked Dec 5, 2023 in Q&A · Unanswered

  

  

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  BRAM Utilization

  AhmadHouraniah asked Aug 14, 2023 in Q&A · Closed · Answered

  

  

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  Please be aware that GCC-7 is no longer supported on Ubuntu 20.04 w.r.t. build compatibility

  tangxifan started Nov 14, 2023 in General

  

  

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  Cannot Pass Ring Oscillator Through OpenFPGA yosys_flow?

  tornupnegatives asked Nov 3, 2023 in Q&A · Unanswered

  

  

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  2 folders with the same(almost) name

  JackOfShadow started Oct 28, 2023 in General

  

  

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  Some strange logic errors related to the netlist generated by OpenFPGA

  Chris202305 asked Sep 14, 2023 in Q&A · Unanswered

  

  

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  Some questions about architecture

  Chris202305 asked Sep 6, 2023 in Q&A · Unanswered

  

  

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  How does the clock pin connect the routing channels?

  aaron941223 asked Jun 24, 2022 in Q&A · Unanswered

  

  

  

  

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  Seeking Recommendations for OpenFPGA Architecture File Generation Tools

  Chris202305 asked Sep 6, 2023 in Q&A · Unanswered

  

  

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  Run task basic_test FAIL

  anhdv2000 asked May 4, 2023 in Q&A · Unanswered

  

  

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  How should I compile a full adder or LED blinking design for ice40 fpga using Open FPGA tools.

  ShubhAgarwal-dev asked Apr 26, 2023 in Q&A · Closed · Unanswered

  

  

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  How to avoid Constant-0 drivers added to undriven nets

  cristianomodesti asked Mar 7, 2023 in Q&A · Unanswered

  

  

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