AFEBioPICO

An Ultra-Low-Power Analog Front-End for Bio-Signals intended to be integrated for the SSCS Platform for IC Design Outreach (PICO) Open-Source Design Contest.

Table of contents

• Summary
  • Motivation
• Description
  • Block Diagram
  • Schematics and Layouts
  • Simulation Results
  • Target Performance Summary
• Team Members
• References

Summary

This design contains an analog signal processing block that:

• filters DC inputs;
• amplifies the AC components with an user selected voltage gain; and
• filters frequencies outside the bio-signals bandwidth.
  

In order to bias the circuit a current reference is also provided. All this process is done while consuming only 5 μW for a 1.8 V supply voltage.

Motivation

As a consequence of the population aging, chronic diseases are becoming the significant cause of death in most countries. Unfortunately, intermittent and asymptomatic features of many chronic disorders turn the task of diagnosis into a real challenge. Due to the new trends of wearable devices for biosensing, predicting and detecting the exact moment that a chronic disease is happening became a possible solution. Hence, it can do a better and timely diagnostic. Therefore, in this project, we propose an ultra-low-power analog front-end to integrate a system for long-term monitoring. We can apply this work to several bio-signals, such as ECG, EMG, and EEG.

Description

The analog front-end for bio-signals main goal is to amplify its inputs, and filter interference and noise without losing resolution, so that the processed signals information can be properly extracted.

Our design is composed of two blocks. The first block, the Low-Power Low-Noise Amplifier (LNA) [1], simultaneously filters the input DC signal and amplifies it. Normally, electrodes output an unknown DC offset which must be canceled, otherwise it would be amplified together with the input signal and saturate the output, causing distortion.

The second and last block is buffer made with a class AB operational amplifier. Its function is to isolate the output load from the LNA, so the LNA characteristics are not affected by it.

Layouts

• All layouts use common-centroid technique
• All wires are shielded, as they are very long and parasitic capacitance between then would be significant. Provides extra protection for noise. Very large parasitic capacitors between signals and the ground plane.

AFE

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Simulation Results

Target Performance Summary

Specifications	-
VDD	1.8-3.3 V
Power	5 μW
Input Noise	10 μV RMS (@ 0.05-100 Hz)
Offset Voltage	1 mV
Gain	10 V/V
Bandwidth	0.5-100 Hz
THD	0.1 % @ 1 Vpp

Status and Issues

• Variable gain was scrapped from project. Only fixed LNA gain is available.
• Pseudo-resistor doesn't have a biasing circuit to correct process variability.
• Documentation is extremely incomplete.

Team members

B.Eng. Deni Germano Alves Neto (Deni) | [email protected] | Linkedin |

M.Sc. João Vitor Testi Ferreira (Testi) | [email protected] | Linkedin |

M.Sc. Luís Henrique Rodovalho (Rodovalho) | [email protected] | Linkedin |

M.Sc. Rafael Sanchotene Silva (Rafael) | [email protected] | Linkedin |

M.Sc. Thiago Daros Fernandes (Thiago) | [email protected] | Linkedin |

References

[1] Harrison, Reid R., et al. "A low-power integrated circuit for a wireless 100-electrode neural recording system." IEEE Journal of Solid-State Circuits 42.1 (2006): 123-133.