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Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

Verilog 56 7 Updated Sep 13, 2024

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

640 76 Updated Dec 27, 2024
Python 1 Updated Jun 14, 2023

SparseP is the first open-source Sparse Matrix Vector Multiplication (SpMV) software package for real-world Processing-In-Memory (PIM) architectures. SparseP is developed to evaluate and characteri…

C 70 10 Updated Jun 29, 2022

IEEE 754 single and double precision floating point library in systemverilog and vhdl

VHDL 61 10 Updated Dec 21, 2024

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

SystemVerilog 446 117 Updated Oct 23, 2024

Functional verification project for the CORE-V family of RISC-V cores.

Assembly 468 228 Updated Jan 2, 2025

The Horizon 2020 Open Transprecision Computing project

6 4 Updated Jan 13, 2021

An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).

C++ 74 13 Updated Jul 26, 2024

A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.

C++ 67 15 Updated Nov 7, 2021

Open, Modular, Deep Learning Accelerator

Scala 265 73 Updated Apr 10, 2024
Tcl 8 Updated May 22, 2023

A flush-reload side channel attack implementation

C++ 42 23 Updated Mar 26, 2022

OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.

Verilog 136 21 Updated Mar 2, 2023

Contains the code examples from The UVM Primer Book sorted by chapters.

SystemVerilog 501 205 Updated Dec 24, 2021

Generator Bootcamp Material: Learn Chisel the Right Way

Jupyter Notebook 995 280 Updated Sep 10, 2024

NucleusRV - A 32-bit 5 staged pipelined risc-v core.

C 61 24 Updated Dec 4, 2024

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,431 559 Updated Dec 20, 2024

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

SystemVerilog 989 428 Updated Jul 19, 2024

Tile based architecture designed for computing efficiency, scalability and generality

SystemVerilog 238 62 Updated Dec 26, 2024

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Scala 1,708 666 Updated Jan 3, 2025

A core language for rule-based hardware design 🦑

Coq 146 11 Updated Oct 13, 2024

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

C 154 83 Updated Dec 23, 2024

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

HTML 404 43 Updated Sep 13, 2024

SHAKTI Multiply-And-Accumulate Accelerator Network (SHAKTIMAAN), IITM's Deep Learning accelerator effort

Bluespec 9 4 Updated Sep 19, 2021

RISC-V Assembly Programmer's Manual

Makefile 1,456 239 Updated Dec 20, 2024

10x faster matrix and vector operations

C++ 2,478 170 Updated Oct 12, 2022
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