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1. Universal-Shift-Register Universal-Shift-Register Public

   This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.

   Verilog 10 1

2. Fault-collapsing-and-Fault-simulation Fault-collapsing-and-Fault-simulation Public

   This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs Dominance fault collapsing, Parallel fault simulation, Deductive fault simulation.

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3. SCOAP-Controllability-and-Observability SCOAP-Controllability-and-Observability Public

   This project is based on Digital VLSI Testing and Testability. The netlist is given as input, the code performs SCOAP Controllability and Observability of circuit..

   Jupyter Notebook 3 1

4. Physical-Design-Issues Physical-Design-Issues Public

   The process of converting the gate-level netlist to layout is termed as physical design. In physical design, there are various stages of design, various mandatory checks in each stage and involved …

5. SODC SODC Public

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