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27 Open 112 Closed
27 Open 112 Closed
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Issues list

GHDL+YOSYS formal verification, using Xilinx primitives
#194 opened Jan 3, 2024 by Marceloqa
1
Error when using plugin on M1 mac
#193 opened Dec 7, 2023 by joaocolombari
1
wire not found for $posedge
#192 opened Nov 12, 2023 by GyrosGeier
3
The project Keccak_PPL has several VHDL compilation issues (Fails to synthesize).
#190 opened Sep 17, 2023 by alaindargelas
The pre-built option #1 is extreamly outdated
#189 opened Sep 11, 2023 by rodrigomelo9
1
Error when using altera_mf lib
#179 opened Nov 14, 2022 by albydnc
4
Error when using inout record
#176 opened Oct 19, 2022 by albydnc
3
Unable to build the plugin
#175 opened Oct 11, 2022 by canerbulduk
3
High impedance assignment translates to 1'x
#170 opened Jul 20, 2022 by DanielG
6
Error building ghdl plugin for yosys question
#168 opened Jun 2, 2022 by minghungumich
12
Roadmap for a release question
#167 opened Feb 4, 2022 by Martoni
1
Use of BRAM in ICE40 ...
#165 opened Jan 8, 2022 by PPlinux
2
Another case of "wire not found for $posedge" - related to async resets?
#164 opened Jan 5, 2022 by robinsonb5
3
wire not found for $posedge
#163 opened Dec 31, 2021 by kammoh
3
VHDL to Verilog conversion with yosys-ghdl-plugin -- how to perserve signal names
#153 opened Aug 10, 2021 by 71GA
4
Add support for Yosys $live cell (needed for liveness proofs)
#152 opened Aug 3, 2021 by tmeissner
2
ERROR: wire not found for $posedge
#146 opened Mar 30, 2021 by stevenbell
3
GHDL synth internal state inconsistent with Yosys state
#137 opened Nov 2, 2020 by rlee287
6
Mixed synthesis with a Verilog top-level fails when parameters are specified
#136 opened Oct 11, 2020 by rodrigomelo9
2
Multiple use of module
#131 opened Sep 8, 2020 by IIupor
2
"ERROR: wire not found for $posedge" when synthesizing dynamic array insertion
#130 opened Aug 22, 2020 by Xiretza
12
Testing on some designs from Opencores
#126 opened Jun 18, 2020 by Chopper455
4
Improve conversion of records
#120 opened May 17, 2020 by ozbenh
3
Feature suggestion: add a ghdl_write_vhdl command to yosys through the plugin Good first issue
#112 opened Apr 22, 2020 by rlee287
5
Make test logs and exit codes consistent
#79 opened Jan 19, 2020 by eine
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