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Updated the layout to properly use the metal resistors in front of
pins that are connected to the same net. Updated the GDS with this change, and also to properly generate hierarchical layers, which apparently had not been done previously. Verilog and schematic have not yet been updated with the metal resistor change, and so will fail LVS until they are.
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Original file line number | Diff line number | Diff line change |
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@@ -1,13 +1,18 @@ | ||
magic | ||
tech sky130A | ||
magscale 1 2 | ||
timestamp 1620310959 | ||
use example_por example_por_0 | ||
timestamp 1620310959 | ||
transform -1 0 11285 0 1 -14 | ||
box 0 0 11344 8338 | ||
timestamp 1639841760 | ||
<< error_p >> | ||
rect 5036 7870 5051 7898 | ||
rect 5008 7676 5023 7870 | ||
rect 20366 7862 20381 7890 | ||
rect 20394 7668 20409 7862 | ||
use example_por example_por_1 | ||
timestamp 1620310959 | ||
timestamp 1639841760 | ||
transform 1 0 14132 0 1 -22 | ||
box 0 0 11344 8338 | ||
use example_por example_por_0 | ||
timestamp 1639841760 | ||
transform -1 0 11285 0 1 -14 | ||
box 0 0 11344 8338 | ||
<< end >> |
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