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add wishbone test #24

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mattvenn opened this issue Mar 10, 2022 · 3 comments
Open

add wishbone test #24

mattvenn opened this issue Mar 10, 2022 · 3 comments
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@marwaneltoukhy @M0stafaRady
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simulation Verilog testbenches and simulation

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@mattvenn
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Add a new test that should currently fail with the narrow address range.
The full address range is meant to be 0x3000_0000 to 0x3fff_ffff

@suppamax

caravel_mgmt_soc_litex/verilog/dv/tests-standalone/Makefile

Line 23 in 3fee299

all: ${BLOCKS}

@mattvenn
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Matt to add a warning in the docs

@suppamax
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See PR #27

@suppamax suppamax mentioned this issue Mar 23, 2022
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@jeffdi jeffdi moved this to Todo in Caravel Redesign Sep 27, 2022
@RTimothyEdwards RTimothyEdwards added enhancement New feature or request simulation Verilog testbenches and simulation and removed enhancement New feature or request labels Oct 4, 2022
@marwaneltoukhy
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This has a trail of PRs and they all end up with an invalid tag. I think this should be closed and reopen another PR/issue if still needed.

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@marwaneltoukhy marwaneltoukhy

@M0stafaRady M0stafaRady

Labels
simulation Verilog testbenches and simulation
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Caravel Redesign
Status: Todo
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@mattvenn @RTimothyEdwards @suppamax @marwaneltoukhy @M0stafaRady