Fix power guards

manifest

@@ -20,7 +20,7 @@ fa26aa34b4b382aacad9b7ac07a36b17172a401f  verilog/rtl/caravel.v
 1bbaa93405d4cb51429eacea4da40014231b11ed  verilog/rtl/caravel_motto.v
 ae07f0d87e69f4dd2026ed841e3a962facac847b  verilog/rtl/caravel_openframe.v
 d97cb60c8d125d6098111d4f0aa00410515770eb  verilog/rtl/caravel_power_routing.v
-bc1e961e41d1d3a383a018279a08bf4108911f53  verilog/rtl/chip_io.v
+66cd4cc70097aa0a0666d0105712affa140a3977  verilog/rtl/chip_io.v
 f2242e1f295ee5efeacea51698f706a2cfd97c28  verilog/rtl/chip_io_alt.v
 09740344da1a9bb76438165247c49b4795b94b9b  verilog/rtl/chip_io_openframe.v
 126aff02aa229dc346301c552d785dec76a4d68e  verilog/rtl/clock_div.v
@@ -48,9 +48,9 @@ e0c6ead5e35c1ba01d923c482e953c2af9691524  verilog/rtl/mprj_io_buffer.v
 3baffde4788f01e2ff0e5cd83020a76bd63ef7d7  verilog/rtl/mprj_logic_high.v
 5287821a0ed1994850a978ef0cd024fac51fb6e8  verilog/rtl/open_source.v
 33c8fc54298e5425875aaab8c139074ec7d0e9e9  verilog/rtl/openframe_netlists.v
-4edbfd0ad80b69a799a399ffc717b560fcae615b  verilog/rtl/pads.v
+51f7c21d36076958a145a1ff8f4947b147e54fd4  verilog/rtl/pads.v
 669d16642d5dd5f6824812754db20db98c9fe17b  verilog/rtl/ring_osc2x13.v
-739ca5ed63a513d2e4c9bf3ecfad32d9fa527518  verilog/rtl/simple_por.v
+83937790b8f5dbcdd7e9a804b5e9bdf475c0ab7d  verilog/rtl/simple_por.v
 b9d6114a5067a04dd59cdd46fb988591c16743ce  verilog/rtl/spare_logic_block.v
 8f0bec01c914efe790a09ffe62bbfe0781069e35  verilog/rtl/xres_buf.v
 256190717faa72005cf7656d8443c4c0693b3f78  scripts/set_user_id.py

verilog/rtl/chip_io.v

@@ -276,8 +276,10 @@ module chip_io(
     wire [6:0] vssd_const_zero;	// Constant value for management pins
 
     constant_block constant_value_inst [6:0] (
+	`ifdef USE_POWER_PINS
 	.vccd(vccd),
 	.vssd(vssd),
+	`endif // USE_POWER_PINS
 	.one(vccd_const_one),
 	.zero(vssd_const_zero)
     );

verilog/rtl/pads.v

@@ -45,7 +45,7 @@
 
 	`define MGMT_ABUTMENT_PINS \
 	.AMUXBUS_A(analog_a),\
-	.AMUXBUS_B(analog_b),\
+	.AMUXBUS_B(analog_b), `ifdef USE_POWER_PINS \
 	.VSSA(vssa),\
 	.VDDA(vdda),\
 	.VSWITCH(vddio),\
@@ -55,7 +55,7 @@
 	.VCCD(vccd),\
 	.VSSIO(vssio),\
 	.VSSD(vssd),\
-	.VSSIO_Q(vssio_q),
+	.VSSIO_Q(vssio_q), `endif
 `else 
 	`define USER1_ABUTMENT_PINS 
 	`define USER2_ABUTMENT_PINS 

verilog/rtl/simple_por.v

@@ -44,12 +44,19 @@ module simple_por(
     // down.  Note that this is sped way up for verilog simulation;  the
     // actual circuit is set to a 15ms delay.
 
-    always @(posedge vdd3v3) begin
+    `ifdef USE_POWER_PINS
+        always @(posedge vdd3v3) begin
+    `else
+        initial begin
+    `endif
 	#500 inode <= 1'b1;
     end
-    always @(negedge vdd3v3) begin
-	#500 inode <= 1'b0;
-    end
+
+    `ifdef USE_POWER_PINS
+        always @(negedge vdd3v3) begin
+        #500 inode <= 1'b0;
+        end
+    `endif
 
     // Instantiate two shmitt trigger buffers in series