update caravel_core openlane configs with the mgmt_soc with DFT

openlane/caravel_core/openlane2-command.bash

@@ -0,0 +1,5 @@
+export RUN_TAG=RUN_15
+rm -rf /home/hosni/caravel-3/caravel/openlane/caravel_core/runs/$RUN_TAG
+export DEFINE_CLOCKS=0 ; python3 -m openlane /home/hosni/caravel-3/caravel/openlane/caravel_core/config.json /home/hosni/caravel-3/caravel/openlane/caravel_core/macros.json --run-tag $RUN_TAG --to OpenROAD.CTS --log-level WARNING
+export DEFINE_CLOCKS=1 ; python3 -m openlane /home/hosni/caravel-3/caravel/openlane/caravel_core/config.json /home/hosni/caravel-3/caravel/openlane/caravel_core/macros.json --run-tag $RUN_TAG --from OpenROAD.ResizerTimingPostCTS --to OpenROAD.RCX --log-level WARNING
+python3 -m openlane /home/hosni/caravel-3/caravel/openlane/caravel_core/config.json /home/hosni/caravel-3/caravel/openlane/caravel_core/macros-sta.json --run-tag $RUN_TAG --from OpenROAD.STAPostPNR --log-level WARNING

openlane/caravel_core/pdn_configuration/pdn.tcl

@@ -43,11 +43,11 @@ foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
 set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
     -secondary_power $secondary
 
-    define_pdn_grid \
-        -name stdcell_grid \
-        -starts_with POWER \
-        -voltage_domain CORE \
-        -pins "met4 met5"
+define_pdn_grid \
+    -name stdcell_grid \
+    -starts_with POWER \
+    -voltage_domain CORE \
+    -pins "met3 met4 met5"
 
 ####  core ring   ####
 add_pdn_stripe \
@@ -130,7 +130,7 @@ add_pdn_stripe \
         -layer met5 \
         -width 6.4 \
         -pitch 100 \
-        -offset 200 \
+        -offset 205 \
         -spacing 2.4 \
         -nets "vccd vssd" \
         -starts_with POWER
@@ -162,7 +162,7 @@ add_pdn_stripe \
         -layer met5 \
         -width 4.8 \
         -pitch 120 \
-        -offset 827 \
+        -offset 844.3 \
         -spacing 3.2 \
         -number_of_straps 1 \
         -nets "vccd1 vssd1 vccd2 vssd2 vdda1 vssa1 vdda2 vssa2" \
@@ -248,9 +248,19 @@ add_pdn_stripe \
     add_pdn_stripe \
         -grid stdcell_grid \
         -layer met5 \
-        -width 5 \
-        -pitch 14 \
-        -offset 137 \
+        -width 6 \
+        -pitch 34 \
+        -offset 110.5 \
+        -spacing 2 \
+        -number_of_straps 2 \
+        -nets "vddio vssio" \
+        -starts_with POWER
+    add_pdn_stripe \
+        -grid stdcell_grid \
+        -layer met4 \
+        -width 4.8 \
+        -pitch 386 \
+        -offset 2641 \
         -spacing 2 \
         -number_of_straps 2 \
         -nets "vddio vssio" \
@@ -260,17 +270,32 @@ add_pdn_stripe \
         -layer met4 \
         -width 4.8 \
         -pitch 386 \
-        -offset 647 \
+        -offset 665 \
         -spacing 2 \
         -number_of_straps 2 \
         -nets "vddio vssio" \
         -starts_with POWER
 
+## mprj connections
+add_pdn_stripe \
+    -grid stdcell_grid \
+    -layer met3 \
+    -width 2.4 \
+    -pitch 100 \
+    -offset 1200 \
+    -spacing 2 \
+    -number_of_straps 34 \
+    -nets "vccd1 vssd1 vccd2 vssd2 vssa1 vdda1 vdda2 vssa2" \
+    -starts_with POWER
 
 add_pdn_connect \
     -grid stdcell_grid \
     -layers "met4 met5"
 
+add_pdn_connect \
+    -grid stdcell_grid \
+    -layers "met3 met4"
+
 # Adds the standard cell rails if enabled.
 if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
     add_pdn_stripe \
@@ -290,7 +315,7 @@ define_pdn_grid \
     -default \
     -name macro \
     -starts_with POWER \
-    -halo "5 5"
+    -halo "1 0.8"
 
 add_pdn_connect \
     -grid macro \

openlane/caravel_core/sdc_files/base.sdc

@@ -1,26 +1,42 @@
-### Caravel Signoff SDC
+### Caravel base SDC
 ### Rev 3
-### Date: 28/10/2022
+### Date: 3/12/2022
 
-## MASTER CLOCKS
-create_clock -name clk -period 18 [get_pins {clock_ctrl/core_clk}] 
-# create_clock -name clk -period 25 [get_ports {clock_core}] 
+if {$::env(DEFINE_CLOCKS) == 1} {
+   ## MASTER CLOCKS
+   # create_clock -name clk -period 25 [get_ports {clock_core}] 
+   create_clock -name clk -period 25 [get_pins {clock_ctrl/core_clk}] 
 
-set_clock_uncertainty 0.5 [get_clocks {clk}] 
+   create_clock -name hk_serial_clk -period 50 [get_pins {housekeeping/serial_clock}]
+   create_clock -name hk_serial_load -period 1000 [get_pins {housekeeping/serial_load}]
+   # hk_serial_clk period is x2 core clock
 
-set_propagated_clock [get_clocks {clk}]
+   set_clock_uncertainty 0.200 [get_clocks {clk}] 
+   set_clock_uncertainty 0.100 [get_clocks {hk_serial_clk hk_serial_load}]
 
-## INPUT/OUTPUT DELAYS
-set input_delay_value 4
-set output_delay_value 20
-puts "\[INFO\]: Setting output delay to: $output_delay_value"
-puts "\[INFO\]: Setting input delay to: $input_delay_value"
-# set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [all_inputs]
-set_input_delay 0  -clock [get_clocks {clk}] [get_ports {clock_core}]
-set_input_delay 1  -clock [get_clocks {clk}] [get_ports {flash_io0_di}]
-set_input_delay 1  -clock [get_clocks {clk}] [get_ports {flash_io1_di}]
+   set_clock_groups \
+      -name clock_group \
+      -logically_exclusive \
+      -group [get_clocks {clk}]\
+      -group [get_clocks {hk_serial_clk}]\
+      -group [get_clocks {hk_serial_load}]
 
-# set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [all_outputs]
+   set_propagated_clock [get_clocks {clk}]
+   set_propagated_clock [get_clocks {hk_serial_clk}]
+   set_propagated_clock [get_clocks {hk_serial_load}]
+
+   ## INPUT/OUTPUT DELAYS
+   set input_delay_value 4
+   set output_delay_value 20
+   puts "\[INFO\]: Setting output delay to: $output_delay_value"
+   puts "\[INFO\]: Setting input delay to: $input_delay_value"
+   set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [all_inputs]
+   set_input_delay 0  -clock [get_clocks {clk}] [get_ports {clock_core}]
+   set_input_delay -2 -clock [get_clocks {clk}] [get_ports {flash_io0_di}]
+   set_input_delay -2 -clock [get_clocks {clk}] [get_ports {flash_io1_di}]
+
+   set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [all_outputs]
+} 
 
 ## MAX FANOUT
 set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
@@ -43,13 +59,10 @@ set_input_transition -min $min_in_tran [all_inputs]
 set_input_transition -max $max_in_tran [all_inputs]
 
 # derates
-set derate 0.15
+set derate 0.06
 puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %"
 set_timing_derate -early [expr 1-$derate]
 set_timing_derate -late [expr 1+$derate]
 
 ## MAX transition/cap
-set_max_trans 0.9 [current_design]
-# set_max_cap 0.5 [current_design]
-
-# group_path -weight 100 -through [get_pins mprj/la_data_out[0]] -name mprj_floating
+set_max_trans 0.90 [current_design]

openlane/caravel_core/sdc_files/signoff.sdc

@@ -26,26 +26,35 @@ set_propagated_clock [get_clocks {hk_serial_clk}]
 set_propagated_clock [get_clocks {hk_serial_load}]
 
 ## INPUT/OUTPUT DELAYS
-# set input_delay_value 10
-# set output_delay_value 10
-# puts "\[INFO\]: Setting output delay to: $output_delay_value"
-# puts "\[INFO\]: Setting input delay to: $input_delay_value"
-# set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [all_inputs]
-# set_input_delay 0  -clock [get_clocks {clk}] [get_ports {mprj_io_in[35]}]
-# set_input_delay 0  -clock [get_clocks {clk}] [get_ports {clock_core}]
-# set_input_delay 1  -clock [get_clocks {clk}] [get_ports {flash_io0_di}]
-# set_input_delay 1  -clock [get_clocks {clk}] [get_ports {flash_io1_di}]
-# set_input_delay -8 -clock [get_clocks {debug_clk}] [get_ports {mgmt_io_in[0]}]
-# 
-# set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [all_outputs]
-# set_output_delay 21 -clock [get_clocks {debug_clk}] [get_ports {mgmt_io_out[0]}]
+set input_delay_value 4
+set output_delay_value 4
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+set_input_delay $input_delay_value  -clock [get_clocks {clk}] -add_delay [all_inputs]
+set_input_delay 0  -clock [get_clocks {clk}] [get_ports {mprj_io_in[35]}]
+set_input_delay 0  -clock [get_clocks {clk}] [get_ports {clock_core}]
+set_input_delay 2.5 -clock [get_clocks {clk}] [get_ports {flash_io0_di}]
+set_input_delay 2.5 -clock [get_clocks {clk}] [get_ports {flash_io1_di}]
+set_input_delay -2 -clock [get_clocks {debug_clk}] [get_ports {mgmt_io_in[0]}]
+
+set_output_delay $output_delay_value  -clock [get_clocks {clk}] -add_delay [all_outputs]
+set_output_delay 21 -clock [get_clocks {debug_clk}] [get_ports {mgmt_io_out[0]}]
 
 ## MAX FANOUT
 set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
 
 ## FALSE PATHS (ASYNCHRONOUS INPUTS)
 set_false_path -from [get_ports {rstb_h}]
 
+## MULTI CYCLE PATHS
+# Multicycle paths
+set_multicycle_path -setup 2 -through [get_pins {mprj/wbs_ack_o}]
+set_multicycle_path -hold 1  -through [get_pins {mprj/wbs_ack_o}]
+set_multicycle_path -setup 2 -through [get_pins {mprj/wbs_cyc_i}]
+set_multicycle_path -hold 1  -through [get_pins {mprj/wbs_cyc_i}]
+set_multicycle_path -setup 2 -through [get_pins {mprj/wbs_stb_i}]
+set_multicycle_path -hold 1  -through [get_pins {mprj/wbs_stb_i}]
+
 # add loads for output ports (pads)
 set min_cap 0.5
 set max_cap 1.0
@@ -54,14 +63,14 @@ puts "\[INFO\]: Cap load range: $min_cap : $max_cap"
 set_load -min $min_cap [all_outputs] 
 set_load -max $max_cap [all_outputs] 
 
-set min_in_tran 1
-set max_in_tran 1.49
+set min_in_tran 0.6
+set max_in_tran 1.2
 puts "\[INFO\]: Input transition range: $min_in_tran : $max_in_tran"
 set_input_transition -min $min_in_tran [all_inputs] 
 set_input_transition -max $max_in_tran [all_inputs]
 
 # derates
-set derate 0.0375
+set derate 0.05
 puts "\[INFO\]: Setting derate factor to: [expr $derate * 100] %"
 set_timing_derate -early [expr 1-$derate]
 set_timing_derate -late [expr 1+$derate]