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470 Open 486 Closed
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Issues list

Formatter splits label from assertion on new line unnecessarily formatter Verilog code formatter issues
#2284 opened Oct 18, 2024 by hankhsu1996
Confusion on camelCase versus PascalCase enhancement New feature or request style-linter Verilog style-linter issues
#2283 opened Oct 12, 2024 by ukanuk
Improve lint rule help enhancement New feature or request good first issue Good for newcomers style-linter Verilog style-linter issues
#2278 opened Oct 6, 2024 by IEncinas10
how to use AUTO-expansion in vscode ? formatter Verilog code formatter issues
#2258 opened Sep 25, 2024 by cheungxi
Alias -i to --inplace formatter Verilog code formatter issues
#2257 opened Sep 25, 2024 by wsnyder
invalid-system-task-function not checked if multiple ifdefs are present in file style-linter Verilog style-linter issues
#2256 opened Sep 24, 2024 by matlupi
3
Getting Error Unsupported: timing control statement in this location, for wait and @(posedge) statements language-server Language server related issues
#2253 opened Sep 19, 2024 by v4ibhav
3
localparam type (...) recognized as wrong syntax rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2249 opened Sep 15, 2024 by goekce
Include formatter in VS Code Extension language-server Language server related issues
#2245 opened Aug 28, 2024 by puppuccino
parser refuses bit-selection of concatenation rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2244 opened Aug 27, 2024 by matlupi
1
Misalignment with comments that end with backslash "\" formatter Verilog code formatter issues
#2243 opened Aug 27, 2024 by Stavegu
1
Array assignment to wires - parse error on = rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2240 opened Aug 21, 2024 by hzeller
1
adding a setting for comment alignment enhancement New feature or request style-linter Verilog style-linter issues
#2239 opened Aug 21, 2024 by 12113004
It is not possible to format the code shown below formatter Verilog code formatter issues
#2238 opened Aug 19, 2024 by 17Reset
4
Is it possible to leave all lines whose beginning wasn't moved as they are? (i.e. to prevent any internal indentation within the line) formatter Verilog code formatter issues
#2237 opened Aug 18, 2024 by avidan-efody
Verible's parser accepts incorrect program/module creation rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2233 opened Aug 9, 2024 by luizademelo
using tick define for delay doesn't work rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2232 opened Aug 7, 2024 by vanjoe
Detect data type and rvalue width mismatches enhancement New feature or request style-linter Verilog style-linter issues
#2231 opened Aug 5, 2024 by benjamin051000
How to obtain all symbol tables through textDocumentSymbol request rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2228 opened Aug 5, 2024 by wxllllll
Why is $random considered a "forbidden system function or task"?
#2221 opened Aug 2, 2024 by benjamin051000
2
support for different type rule into kPortDeclaration enhancement New feature or request style-linter Verilog style-linter issues
#2220 opened Aug 2, 2024 by Brughy
Obfuscation tool is obfuscating DEFINES being used formatter Verilog code formatter issues
#2219 opened Aug 1, 2024 by ygiladTT
It Can NOT preprocess properly in SystemVerilog files? style-linter Verilog style-linter issues
#2217 opened Jul 17, 2024 by zpxy
1
Preprocessor Documentation issue rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2215 opened Jul 13, 2024 by a-kest
2
Dynamic code with macros is not parsed properly rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#2197 opened Jun 11, 2024 by bhappel-ciena
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