This is a template project to demonstrate Chisel functionality using the the Scala Bleep build tool.

The project includes a simple module (to be replaced with your design) and also have a test spec written with the scalatest and chiseltest frameworks. The repository also have a GitHub Action to run automated tests on main branch and PRs.

Chisel Learning Resources:

• Chisel Book
• Chisel Documentation
• Chisel API

Software requirements:

• Bleep build tool

• Firtool, the Chisel Firttl compiler

• Verilator (as an option for simulation) - Optional

• GTKWave (to visualize VCD files) - Optional

Installing the Requirements

I recommend using Coursier to manage all installation tooling related to Scala as it will download a Java SDK and the build tool:

On Windows, download and install using the Windows Installer.

# For Linux
curl -fL "https://github.com/coursier/launchers/raw/master/cs-x86_64-pc-linux.gz" | gzip -d > cs
# For MacOS
curl -fL https://github.com/coursier/launchers/raw/master/cs-x86_64-apple-darwin.gz | gzip -d > cs

chmod +x cs
./cs setup

# Install Bleep build tool:
cs install --channel https://raw.githubusercontent.com/oyvindberg/bleep/master/coursier-channel.json bleep

Then install Chisel Firtool that compiles the generated code to SystemVerilog from https://github.com/llvm/circt/releases/latest, downloading the binary for your platform and adding it to the $PATH.

# For MacOS:
curl -sL https://github.com/llvm/circt/releases/download/firtool-1.48.0/firrtl-bin-macos-x64.tar.gz | tar xvz
# For Linux
curl -sL https://github.com/llvm/circt/releases/download/firtool-1.48.0/firrtl-bin-linux-x64.tar.gz | tar xvz
# Export path
export PATH=./firtool-1.48.0/bin:$PATH

Generating SystemVerilog

SystemVerilog code can be generated from Chisel by using the build tool.

bleep run toplevel

The output verilog files are generated in the ./generated directory.

Running tests can be done with:

bleep test