Introduction

This website contains course materials for ECE 4743/6743 – Digital Systems Design. If you see any bugs, please report them!

Resources

General

• Digilent's Basys 3 board and its reference manual

Xilinx

The Basys 3 board contains an Artix-7™ FPGA (Xilinx part number XC7A35T-1CPG236C). This is a member of Xilinx's 7 series, so documentation on either the 7 series or on the Artix applies. Start with the 7 Series FPGAs Overview. Configurable Logic Blocks are the basic building block of FPGAs. Read the 7 Series FPGAs Configurable Logic Block User Guide for the essentials of how the 7 series CLBs work. Next, the DSP slices contain multipliers, adders, and other commonly-used hardware; see the 7 Series FPGAs DSP48E1 Slice User Guide. These FPGAs also contain RAM; see the 7 Series FPGAs Memory Resources User Guide. For more links, see the references on the last page of the 7 Series Product Tables and Product Selection Guide.

Verilog

• The SystemVerilog standard
• Vivado Design Suite User Guide: Synthesis - SystemVerilog Language Support
• (old) See Flop Inferrence in Verilog Synthesis for Xilinx's rules on creating flip-flops in Verilog. Briefly: for an async set/reset, use always @(posedge clk or posedge aset_or_clr).

AXI4 bus

Helpful references:

• The AMBA Specifications, specifically the AMBA AXI and ACE Protocol Specification.
• Xilinx's AMBA AXI4 Interface Protocol provides an overview. They provide a lot of IP cores for AXI4.
• Xilinx AXI tutorials (scroll to "Trending articles"), especially AXI Basics 1 - Introduction to AXI.

AXI4 has separate read and write busses. AXI4 transactions consist of VALID/READY handshakes. From RealDigital (see figures 3 and 4, which appear below), a read transaction:

1. Master: drive address on ARADDR (read address); assert ARVALID (read address is valid).
2. Slave: assert ARREADY (ready for the read address), indicating the slave has the read address. Both may now deassert ARVALID and ARREADY.
3. Slave: drive data on RDATA (read data) and assert RVALID (read data is valid).
4. Master: assert RREADY (ready to read data). In this case, it asserted it earlier, saying it's ready as soon as the slave is.
5. The next rising clock edge completes the transaction. Master may now deassert RREADY; slave may deassert RVALID.

A write transaction:

1. Master: drive address on AWADDR (write address); assert AWVALID (write address is valid).
2. Slave: assert AWREADY (ready for the write address), indicating the it has the write address. Both may now deassert AWVALID and AWREADY.
3. Master: drive data on WDATA (write data); assert WVALID (write data is valid).
4. Slave: assert WREADY (ready for write data), indicating it has the write data. Both may now deassert WVALID and WREADY.
5. Save: drive response on BRESP (write response data) and assert BVALID (write response is valid). The response is OK (2 types) or error (2 types).
6. Master: assert BREADY (ready for write response), indicating that it has the write response.
7. The next rising clock edge completes the transaction. Master may now deassert BREADY; slave may deassert BVALID.