Merge pull request #1 from Wiznet/develop

Release F/W v1.4.1

README.md

@@ -11,11 +11,19 @@ This is the Modbus version repository, see the following link for the MQTT versi
 
 https://github.com/Wiznet/WIZ550S2E
 
-### v1.4.0
+### v1.4.1
+- Second release
+- Changed App build optimization level -O3 to -O1.
+- Changed Boot Makefile generation option.
+- Added watchdog
+	- Set watchdog timeout to 5 seconds.
+- Fixed 'AT+FDNS' bug.
 
+### v1.4.0
 - First release
 - Added features
 	- Modbus
 		- [v1.20 Configuration Tool](https://github.com/Wiznet/WIZnet_Configuration_Tool-Modbus) is required.
+
 ### Old version
 - See the following link. [https://github.com/Wiznet/WIZ550S2E](https://github.com/Wiznet/WIZ550S2E)

WIZ550S2E_App/.cproject

@@ -158,7 +158,7 @@
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/modbus}&quot;"/>
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/src/Application/loopback}&quot;"/>
 								</option>
-								<option id="com.crt.advproject.gcc.exe.release.option.optimization.level.1797076545" name="Optimization Level" superClass="com.crt.advproject.gcc.exe.release.option.optimization.level" value="gnu.c.optimization.level.most" valueType="enumerated"/>
+								<option id="com.crt.advproject.gcc.exe.release.option.optimization.level.1797076545" name="Optimization Level" superClass="com.crt.advproject.gcc.exe.release.option.optimization.level" value="gnu.c.optimization.level.optimize" valueType="enumerated"/>
 								<inputType id="com.crt.advproject.compiler.input.1380003728" superClass="com.crt.advproject.compiler.input"/>
 							</tool>
 							<tool id="com.crt.advproject.gas.exe.release.212299160" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.release">

WIZ550S2E_App/src/ATcmd/cmdrun.c

@@ -995,7 +995,10 @@ void act_fdns(char *url)
 	uint8_t backup;
 	S2E_Packet *value = get_S2E_Packet_pointer();
 	uint8_t dns_server_ip[4], dns_domain_name[50];
-	char str[16];
+	char *str;
+
+	str = malloc(32);
+	memset(str, 0, sizeof(str));
 
 	memcpy(dns_server_ip, value->options.dns_server_ip, sizeof(dns_server_ip));
 	if(url == NULL) {
@@ -1015,7 +1018,7 @@ void act_fdns(char *url)
 			cmd_resp_dump(VAL_NONE, (int8_t *)str);
 			break;
 		}
-		else if(ret == -1) {
+		else if((ret == -1) || (ret == 0)) {
 			sprintf(str, "DNS Timeout\r\n");
 			cmd_resp_dump(VAL_NONE, (int8_t *)str);
 			break;

WIZ550S2E_App/src/Internet/DNS/dns.c

@@ -366,20 +366,29 @@ int8_t parseDNSMSG(struct dhdr * pdhdr, uint8_t * pbuf, uint8_t * ip_from_dns)
 	for (i = 0; i < pdhdr->qdcount; i++)
 	{
 		cp = dns_question(msg, cp);
-   #ifdef _DNS_DEUBG_
-      printf("MAX_DOMAIN_NAME is too small, it should be redfine in dns.h"
-   #endif
-		if(!cp) return -1;
+
+		if(!cp)
+		{
+#ifdef _DNS_DEBUG_
+			printf("MAX_DOMAIN_NAME is too small, it should be redefine in dns.h");
+#endif
+			return -1;
+		}
 	}
 
 	/* Answer section */
 	for (i = 0; i < pdhdr->ancount; i++)
 	{
 		cp = dns_answer(msg, cp, ip_from_dns);
-   #ifdef _DNS_DEUBG_
-      printf("MAX_DOMAIN_NAME is too small, it should be redfine in dns.h"
-   #endif
-		if(!cp) return -1;
+
+		if(!cp)
+		{
+#ifdef _DNS_DEBUG_
+			printf("MAX_DOMAIN_NAME is too small, it should be redefine in dns.h");
+#endif
+			return -1;
+		}
+
 	}
 
 	/* Name server (authority) section */
@@ -523,9 +532,9 @@ int8_t DNS_run(uint8_t * dns_ip, uint8_t * name, uint8_t * ip_from_dns)
 		{
 			if (len > MAX_DNS_BUF_SIZE) len = MAX_DNS_BUF_SIZE;
 			len = recvfrom(DNS_SOCKET, pDNSMSG, len, ip, &port);
-      #ifdef _DNS_DEBUG_
+#ifdef _DNS_DEBUG_
 	      printf("> Receive DNS message from %d.%d.%d.%d(%d). len = %d\r\n", ip[0], ip[1], ip[2], ip[3],port,len);
-      #endif
+#endif
          ret = parseDNSMSG(&dhp, pDNSMSG, ip_from_dns);
 			break;
 		}

WIZ550S2E_App/src/Internet/DNS/dns.h

@@ -64,7 +64,7 @@
  * @todo SHOULD BE defined it equal as or greater than your Domain name lenght + null character(1)
  * @note SHOULD BE careful to stack overflow because it is allocated 1.5 times as MAX_DOMAIN_NAME in stack.
  */
-#define  MAX_DOMAIN_NAME   16       // for example "www.google.com"
+#define  MAX_DOMAIN_NAME   256       // for example "www.google.com"
 
 #define	MAX_DNS_RETRY     2        ///< Requery Count
 #define	DNS_WAIT_TIME     3        ///< Wait response time. unit 1s.

WIZ550S2E_App/src/common.h

@@ -9,7 +9,7 @@
 
 #define MAJOR_VER		1
 #define MINOR_VER		4
-#define MAINTENANCE_VER	0
+#define MAINTENANCE_VER	1
 
 #define SOCK_DATA		0
 #define SOCK_CONFIG		1
@@ -23,6 +23,8 @@
 #define APP_BASE		0x6000
 #define WORK_BUF_SIZE	1024
 
+#define WATCHDOG		1	// 0 : disable, 1 : enable
+
 extern uint8_t op_mode;
 
 #endif

WIZ550S2E_App/src/main.c

@@ -82,6 +82,40 @@ int main(void)
 	SystemCoreClockUpdate();
 	Board_Init();
 
+#if WATCHDOG
+	uint32_t wdtFreq;
+
+	/* Initialize WWDT (also enables WWDT clock) */
+	Chip_WWDT_Init(LPC_WWDT);
+
+	/* Prior to initializing the watchdog driver, the clocking for the
+	   watchdog must be enabled. This example uses the watchdog oscillator
+	   set at a 50KHz (1Mhz / 20) clock rate. */
+	Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_WDTOSC_PD);
+	Chip_Clock_SetWDTOSC(WDTLFO_OSC_1_05, 20);
+
+	/* The WDT divides the input frequency into it by 4 */
+	wdtFreq = Chip_Clock_GetWDTOSCRate() / 4;
+
+	/* Select watchdog oscillator for WDT clock source */
+	Chip_Clock_SetWDTClockSource(SYSCTL_WDTCLKSRC_WDTOSC, 1);
+
+	/* Set watchdog feed time constant to approximately 5s */
+	Chip_WWDT_SetTimeOut(LPC_WWDT, wdtFreq * 1000 * 5);
+
+#if !defined(CHIP_LPC11CXX)
+	/* Configure WWDT to reset on timeout */
+	Chip_WWDT_SetOption(LPC_WWDT, WWDT_WDMOD_WDRESET);
+#endif
+
+	/* Clear watchdog warning and timeout interrupts */
+	Chip_WWDT_ClearStatusFlag(LPC_WWDT, WWDT_WDMOD_WDTOF | WWDT_WDMOD_WDINT);
+
+	/* Clear and enable watchdog interrupt */
+	NVIC_ClearPendingIRQ(WDT_IRQn);
+	NVIC_EnableIRQ(WDT_IRQn);
+#endif	/* WATCHDOG */
+
 	Board_LED_Set(0, false);
 	Board_LED_Set(1, false);
 
@@ -155,6 +189,11 @@ int main(void)
 
 	op_mode = OP_DATA;
 	while (1) {
+#if WATCHDOG
+		/* Start watchdog */
+		Chip_WWDT_Start(LPC_WWDT);
+#endif	/* WATCHDOG */
+
 		if(op_mode == OP_COMMAND) {			// Command Mode
 			atc_run();
 			sockwatch_run();
@@ -174,8 +213,21 @@ int main(void)
 				run_dns = 0;
 			}
 		}
+#if WATCHDOG
+		/* Clear watchdog warning and timeout interrupts */
+		Chip_WWDT_ClearStatusFlag(LPC_WWDT, WWDT_WDMOD_WDTOF | WWDT_WDMOD_WDINT);
+
+		/* Clear and enable watchdog interrupt */
+		NVIC_ClearPendingIRQ(WDT_IRQn);
+		NVIC_EnableIRQ(WDT_IRQn);
+#endif	/* WATCHDOG */
 	}
 
+#if WATCHDOG
+	/* DeInitialize watchdog */
+	Chip_WWDT_DeInit(LPC_WWDT);
+#endif	/* WATCHDOG */
+
 	/* DeInitialize SPI peripheral */
 	Chip_SSP_DeInit(LPC_SSP0);
 

WIZ550S2E_Boot/.cproject

@@ -19,7 +19,7 @@
 					<folderInfo id="com.crt.advproject.config.exe.debug.364555958." name="/" resourcePath="">
 						<toolChain id="com.crt.advproject.toolchain.exe.debug.782992002" name="Code Red MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
 							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1099776849" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
-							<builder buildPath="${workspace_loc:/WIZ550S2E_Boot/Release}" id="com.crt.advproject.builder.exe.debug.734562767" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
+							<builder buildPath="${workspace_loc:/WIZ550S2E_Boot/Release}" id="com.crt.advproject.builder.exe.debug.734562767" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
 							<tool id="com.crt.advproject.cpp.exe.debug.406169110" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug"/>
 							<tool id="com.crt.advproject.gcc.exe.debug.1163164486" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
 								<option id="com.crt.advproject.gcc.arch.304814877" name="Architecture" superClass="com.crt.advproject.gcc.arch" value="com.crt.advproject.gcc.target.cm0" valueType="enumerated"/>

wiznet_s2e_wiz550s2e_board/.cproject

@@ -134,44 +134,44 @@
 	<storageModule moduleId="com.crt.config">
 		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
 &lt;TargetConfig&gt;&#13;
-&lt;Properties property_0="" property_2="LPC11_12_13_128K_8K.cfx" property_3="NXP" property_4="LPC11U37/401" property_count="5" version="70200"/&gt;&#13;
-&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC11U37/401" flash_driver="LPC11_12_13_128K_8K.cfx" match_id="0x00017C40" name="LPC11U37/401" stub="crt_emu_lpc11_13_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC11U37/401&lt;/name&gt;&#13;
-&lt;family&gt;LPC11Uxx&lt;/family&gt;&#13;
+&lt;Properties property_0="" property_2="LPC11_12_13_96K_8K.cfx" property_3="NXP" property_4="LPC11E36/501" property_count="5" version="70200"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&lt;info chip="LPC11E36/501" flash_driver="LPC11_12_13_96K_8K.cfx" match_id="0x00009C41" name="LPC11E36/501" stub="crt_emu_lpc11_13_nxp"&gt;&lt;chip&gt;&lt;name&gt;LPC11E36/501&lt;/name&gt;&#13;
+&lt;family&gt;LPC11Exx&lt;/family&gt;&#13;
 &lt;vendor&gt;NXP (formerly Philips)&lt;/vendor&gt;&#13;
 &lt;reset board="None" core="Real" sys="Real"/&gt;&#13;
 &lt;clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/&gt;&#13;
 &lt;memory can_program="true" id="Flash" is_ro="true" type="Flash"/&gt;&#13;
 &lt;memory id="RAM" type="RAM"/&gt;&#13;
 &lt;memory id="Periph" is_volatile="true" type="Peripheral"/&gt;&#13;
-&lt;memoryInstance derived_from="Flash" id="MFlash128" location="0x0" size="0x20000"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" id="MFlash96" location="0x0" size="0x18000"/&gt;&#13;
 &lt;memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/&gt;&#13;
-&lt;memoryInstance derived_from="RAM" id="RamUsb2" location="0x20004000" size="0x800"/&gt;&#13;
-&lt;peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/&gt;&#13;
-&lt;peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/&gt;&#13;
-&lt;peripheralInstance derived_from="I2C" determined="infoFile" id="I2C" location="0x40000000"/&gt;&#13;
-&lt;peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40004000"/&gt;&#13;
-&lt;peripheralInstance derived_from="USART" determined="infoFile" id="USART" location="0x40008000"/&gt;&#13;
-&lt;peripheralInstance derived_from="CT16B0" determined="infoFile" id="CT16B0" location="0x4000c000"/&gt;&#13;
-&lt;peripheralInstance derived_from="CT16B1" determined="infoFile" id="CT16B1" location="0x40010000"/&gt;&#13;
-&lt;peripheralInstance derived_from="CT32B0" determined="infoFile" id="CT32B0" location="0x40014000"/&gt;&#13;
-&lt;peripheralInstance derived_from="CT32B1" determined="infoFile" id="CT32B1" location="0x40018000"/&gt;&#13;
-&lt;peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/&gt;&#13;
-&lt;peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40038000"/&gt;&#13;
-&lt;peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
-&lt;peripheralInstance derived_from="SSP0" determined="infoFile" id="SSP0" location="0x40040000"/&gt;&#13;
-&lt;peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/&gt;&#13;
-&lt;peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/&gt;&#13;
-&lt;peripheralInstance derived_from="GPIO-PIN-INT" determined="infoFile" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
-&lt;peripheralInstance derived_from="SSP1" determined="infoFile" id="SSP1" location="0x40058000"/&gt;&#13;
-&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" determined="infoFile" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
-&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" determined="infoFile" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
-&lt;peripheralInstance derived_from="USB" determined="infoFile" id="USB" location="0x40080000"/&gt;&#13;
-&lt;peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="RamPeriph2" location="0x20000000" size="0x800"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" id="SRAM1_2" location="0x20004000" size="0x800"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_NVIC" id="NVIC" location="0xe000e000"/&gt;&#13;
+&lt;peripheralInstance derived_from="V6M_DCR" id="DCR" location="0xe000edf0"/&gt;&#13;
+&lt;peripheralInstance derived_from="I2C" id="I2C" location="0x40000000"/&gt;&#13;
+&lt;peripheralInstance derived_from="WWDT" id="WWDT" location="0x40004000"/&gt;&#13;
+&lt;peripheralInstance derived_from="USART" id="USART" location="0x40008000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B0" id="CT16B0" location="0x4000c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT16B1" id="CT16B1" location="0x40010000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B0" id="CT32B0" location="0x40014000"/&gt;&#13;
+&lt;peripheralInstance derived_from="CT32B1" id="CT32B1" location="0x40018000"/&gt;&#13;
+&lt;peripheralInstance derived_from="ADC" id="ADC" location="0x4001c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="PMU" id="PMU" location="0x40038000"/&gt;&#13;
+&lt;peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x4003c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP0" id="SSP0" location="0x40040000"/&gt;&#13;
+&lt;peripheralInstance derived_from="IOCON" id="IOCON" location="0x40044000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40048000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x4004c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="SSP1" id="SSP1" location="0x40058000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x4005c000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40060000"/&gt;&#13;
+&lt;peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x50000000"/&gt;&#13;
 &lt;/chip&gt;&#13;
 &lt;processor&gt;&lt;name gcc_name="cortex-m0"&gt;Cortex-M0&lt;/name&gt;&#13;
 &lt;family&gt;Cortex-M&lt;/family&gt;&#13;
 &lt;/processor&gt;&#13;
-&lt;link href="LPC11Uxx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
+&lt;link href="LPC11Exx_peripheral.xme" show="embed" type="simple"/&gt;&#13;
 &lt;/info&gt;&#13;
 &lt;/infoList&gt;&#13;
 &lt;/TargetConfig&gt;</projectStorage>