Team 20: RISC-V CPU

RISC-V CPU Project for Imperial EIE 2023/24

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Adam El Jaafari, Archisha Garg, Dimitris Alexopoulos, Toby Browne

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Personal Statements

• Adam El Jaafari
• Archisha Garg
• Dimitris Alexopoulos
• Toby Browne

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Milestones

The following goals were reached:

• Single-cycle CPU tag: single_cycle
• Pipelined CPU with hazard detection tag: pipelined_with_hazard
• CPU with cache tag: cache_only
• Pipelined CPU with hazard detection and caching tag: cache_pipeline_v2

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Capabilities

• Full RV32I instruction set support (except AUIPC, FENCE, FENCI.I, SCALL, SBREAK, RDCYCLE, RDCYCLEH, RDTIME, RDTIMEH, RDINSTRET, RDINSTRETH)
• Fully pipelined with hazard detection and direct mapped cache
• 1024 bytes of cache
• 4096 bytes of instruction memory
• 131072 bytes of data memory
• 1 I/O (output) register
• 2 memory mapped I/O (input) ports

Contribution Table

Key: o = Main Contributor; v = Co-Author

Task	Files	Adam	Archisha	Dimitris	Toby
F1 Program	f1.s, f1_tb.cpp			o
Program Counter	pc.sv	o
Instruction Memory	instrmem.sv	o			v
Control Unit	cu.sv	v	o	o	v
ALU	alu.sv			o
Sign Extend	se.sv		o
Data Memory	datamem.sv				o
Top Level	cpu.sv			o	o
Pipeline Registers	fetchff.sv, executeff.sv, memoryff.sv, decodeff.sv	o			o
Hazard Unit	hazard.sv		o		v
Cache	cache.sv	o		o

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Directory Structure

This is the directory structure that was used for the project.

Directory	Use
rtl	SystemVerilog modules
test	F1 lights program and testbench
tb	Testbenches and test programs/data
doc	Documentation and reports
doc/images	Documentation images

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Important Files

These are some files which are important for building/using the project.

File	Description
tb/cpu.sh	Build script for the CPU testbench
test/f1.sh	Build script for the CPU testbench
tb/pdf.hex	Reference program binary
tb/gaussian.mem, tb/triangle.mem, tb/noisy.mem, tb/sine.mem	Reference program data

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Build instructions

In order to build the project once must follow the following instructions. Firstly the correct program has to be loaded in the instruction memory. The following lines must be modified in rtl/instrmem.sv.

Team20/rtl/instrmem.sv

Lines 21 to 25 in 6e9037b

	initial
	begin
	$display("Loading rom.");
	$readmemh("../test/f1.hex", mem_array);
	end

In order to run the F1 lights program, it can be left as. To test the reference program, $readmemh("../test/f1.hex", mem_array) must be changed to $readmemh("../tb/pdf.hex", mem_array). To change the type of signal used in the reference program the following lines need to be changed in the data memory.

Team20/rtl/datamem.sv

Lines 92 to 96 in 6e9037b

	initial
	begin
	$display("Loading data memory.");
	$readmemh("../tb/gaussian.mem", mem_array, 'h10000);
	end

The line $readmemh("../tb/gaussian.mem", mem_array, 'h10000) must be changed. The path ../tb/gaussian.mem needs to be changed to point to the file you want to use, e.g. ../tb/triangle.mem

After the memory has been configured the following commands need to be ran.

Reference Program

Before running ensure cwd (current working directory) is the root of the repository.

cd tb
./cpu.sh

The trace can be viewed by running:

gtkwave cpu.vcd

F1 Lights

Before running ensure cwd (current working directory) is the root of the repository.

cd test
./f1.sh

The trace can be viewed by running:

gtkwave cpu.vcd

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Results

Below you can see videos of VBuddy running the reference programme and the F1 lights program, as well as the corresponding traces. The images are linked to videos showing the operation so please click them.

Reference Program

Noisy

Gaussian

Triangle

Sine

F1 Lights Program

Counter

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Licensing

The project has been open-source licensed under a BSD-3-Clause license for educational purposes. This does not inlcude the reference program tb/pdf.s and it's associated *.mem files, as well as the tb/vbuddy.cpp file. Copyright for the previously mentioned files is attributed to Peter Y. K. Cheung and thus the license does not apply to them.