Move the glossary aswell as expending it with branches

source/VexiiRiscv/Introduction/index.rst

@@ -18,6 +18,57 @@ Here is a list of links to resources which present or document VexiiRiscv :
 - COSCUP 2024 : https://coscup.org/2024/en/session/PVAHAS
 - ORConf 2024 : https://fossi-foundation.org/orconf/2024#vexiiriscv--a-debian-demonstration
 
+Glossary
+------------------
+
+Here is a few acronyms commonly used across the documentation :
+
+- **CPU** : Central Processing Unit
+- **HART** : Hardware Thread. One CPU core can for instance implement multiple HART, meaning that it will execute multiple threads concurently.
+  For instance, most modern PC CPUs implements 2 Hardware Thread per CPU core (this feature is called hyper-threading)
+- **RF** : Register file
+- **CSR** : Control Status Register, those are the special register in the CPU which allows to handle interruptions, exceptions aswell as configuring things like the MMU.
+- **ALU** : Arithmetic Logical Unit
+- **FPU** : Floating Point Unit
+- **LSU** : Load Store Unit
+- **AMO** : Atomic Memory Operation
+- **MMU** : Memory Management Unit. Translate virtual addresses into pyhsical ones, aswell as check access permitions.
+- **PMP** : Physical Memory Protection. Check physical address access permitions.
+- **I$** : Instruction Cache
+- **D$** : Data Cache
+- **IO** : Input Output. Most of the time it mean LOAD/Store instruction which target peripherals (instead of general purpose memory)
+- **PC** : Program Counter. The address at which the CPU is currently executing instructions.
+
+Here is a few more terms commonly used in the CPU context:
+
+- **Fetching** : The act of reading the data which contains the instructions from the memory.
+- **Decoding** : Figuring out what should be done in the CPU for a given instruction.
+- **Dispatching** : Sending a given instruction to one execution units, once all its dependencies are available.
+- **Executing** : Processing the data used by an instruction
+- **Commiting** : Going past the point were a given instruction can not be canceled/reverted anymore.
+- **Trap** : A trap is an event which will stop the execution of the current software, and make the CPU start executing the software pointed by its trap vector.
+- **Interrupt** : An interrupt is a kind of trap which is generaly comming from the outside. Ex :  timer, GPIO, UART, Ethernet, ...
+- **Exception** : An exception is a kind of trap which is generated by the program the CPU is currently running, for instance an misaligned memory load, a breakpoint, ...
+
+Here is a few more terms commonly used when talking about caches :
+
+- **Line** : A cache line is a block of memory in the cache (typicaly 64 bytes) which will act as a temporary copy of the main memory.
+- **Way** : The number of ways in a CPU specifies how many cache lines could be used to map a given address interchangeably.
+  A high number of ways gives the CPU more choices, when a new cache line need to be allocated, to evict the least usefull cache line.
+- **Set** : The number of sets specifies how parts of the cache lines addresses are staticaly mapped to portions of the memory.
+- **Refill** : The action which load a cache line with a new memory copy
+- **Writeback** : The action which free a modified cache line by writting is back to the main memory
+- **Blocking** : A blocking cache will not accept any new CPU request while performing a refill or a writeback
+- **Prefetching** : Anticipating future CPU needs by refilling yet unrequested memory blocks in the cache (driven by predictions)
+
+Here is a few more terms commonly used when talking about branch prediction :
+
+- **BTB** : Branch Target Buffer. The goal of this hardware unit is to predict what instructions are at a given memory address.
+  ex : Could it be a branch or a jump ? If it is, where would it branch/jump toward ?
+- **RAS** : Return Address Stack. Used to predict where return instruction should jump,
+  by implementing a stack which is pushed on call instructions, and popped on ret instructions.
+- **GShare** : This is a branch prediction technique which try to correlate branche instruction addresses,
+  the CPU history of taken/non-taken branches and a table of taken/non-taken bias to predict future branch instruction behaviour.
 
 Technicalities
 ------------------------------
@@ -89,48 +140,6 @@ RISC-V has 4 main specification :
 
 To figure out more about those specification, check https://riscv.org/technical/specifications/
 
-Glossary
-------------------
-
-Here is a few acronyms commonly used across the documentation :
-
-- **CPU** : Central Processing Unit
-- **HART** : Hardware Thread. One CPU core can for instance implement multiple HART, meaning that it will execute multiple threads concurently.
-  For instance, most modern PC CPUs implements 2 Hardware Thread per CPU core (this feature is called hyper-threading)
-- **RF** : Register file
-- **CSR** : Control Status Register, those are the special register in the CPU which allows to handle interruptions, exceptions aswell as configuring things like the MMU.
-- **ALU** : Arithmetic Logical Unit
-- **FPU** : Floating Point Unit
-- **LSU** : Load Store Unit
-- **AMO** : Atomic Memory Operation
-- **MMU** : Memory Management Unit. Translate virtual addresses into pyhsical ones, aswell as check access permitions.
-- **PMP** : Physical Memory Protection. Check physical address access permitions.
-- **I$** : Instruction Cache
-- **D$** : Data Cache
-- **IO** : Input Output. Most of the time it mean LOAD/Store instruction which target peripherals (instead of general purpose memory)
-
-Here is a few more terms commonly used in the CPU context:
-
-- **Fetching** : The act of reading the data which contains the instructions from the memory.
-- **Decoding** : Figuring out what should be done in the CPU for a given instruction.
-- **Dispatching** : Sending a given instruction to one execution units, once all its dependencies are available.
-- **Executing** : Processing the data used by an instruction
-- **Commiting** : Going past the point were a given instruction can not be canceled/reverted anymore.
-- **Trap** : A trap is an event which will stop the execution of the current software, and make the CPU start executing the software pointed by its trap vector.
-- **Interrupt** : An interrupt is a kind of trap which is generaly comming from the outside. Ex :  timer, GPIO, UART, Ethernet, ...
-- **Exception** : An exception is a kind of trap which is generated by the program the CPU is currently running, for instance an misaligned memory load, a breakpoint, ...
-
-Here is a few more terms commonly used when talking about caches :
-
-- **Line** : A cache line is a block of memory in the cache (typicaly 64 bytes) which will act as a temporary copy of the main memory.
-- **Way** : The number of ways in a CPU specifies how many cache lines could be used to map a given address interchangeably.
-  A high number of ways gives the CPU more choices, when a new cache line need to be allocated, to evict the least usefull cache line.
-- **Set** : The number of sets specifies how parts of the cache lines addresses are staticaly mapped to portions of the memory.
-- **Refill** : The action which load a cache line with a new memory copy
-- **Writeback** : The action which free a modified cache line by writting is back to the main memory
-- **Blocking** : A blocking cache will not accept any new CPU request while performing a refill or a writeback
-- **Prefetching** : Anticipating future CPU needs by refilling yet unrequested memory blocks in the cache (driven by predictions)
-
 About VexRiscv (not VexiiRiscv)
 -------------------------------