Ngi #1095
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Ngi #1095
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The tests are located in qucs/tests now
Trying to port tests from modular Qucs to develop Qucs. For now only testing whether loading schematics without crashing works, next will be to export the netlist from the schematics and see whether it's broken.
This reverts commit a093183.
Ported some reading writing tests from modular qucs to main develop qucs and introduced tests for reading schematics and writing out Verilog netlists. This is a preparation for testing how to write out schematics using Verilog.
Making the tests properly determine the current Qucs version and handing config.h generation properly within CMake
In order to test more effectively the functions for writing netlists and printing are being put in its separate .la library so that it can be directly used by the tests
BUG: connections are wrong, e.g. -Pac:P1 _net0 _net0 Num="1" Z="100 Ohm" P="0 dBm" f="1 GHz" Temp="26.85" -L:L1 _net1 _net1 L="1.2uH" I="" -L:L2 _net2 _net2 L="470nH" I="" -C:C1 _net3 _net3 C="270pF" V="" -C:C2 _net4 _net4 C="270pF" V="" -L:L3 _net5 _net5 L="470nH" I="" -.SP:SP1 Type="log" Start="1MHz" Stop="100MHz" Points="1001" Noise="no" NoiseIP="1" NoiseOP="2" saveCVs="no" saveAll="no" +Pac:P1 _net12 gnd Num="1" Z="100 Ohm" P="0 dBm" f="1 GHz" Temp="26.85" +L:L1 _net41 _net7 L="1.2uH" I="" +L:L2 _net7 _net5 L="470nH" I="" +C:C1 _net6 _net41 C="270pF" V="" +C:C2 _net8 _net7 C="270pF" V="" +L:L3 _net22 _net41 L="470nH" I=""
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Those patches introduce proper testing in Qucs:
Now it tests: